參數(shù)資料
型號: TS80C51RA2
廠商: Atmel Corp.
英文描述: GT 47C 7#12 40#16 PIN PLUG
中文描述: 高性能8位微控制器
文件頁數(shù): 54/74頁
文件大?。?/td> 903K
代理商: TS80C51RA2
54
Rev. C - 06 March, 2001
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
Figure 18. Set-Up Modes Configuration
8.3.3. Programming Algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.
To program the TS87C51RB2/RC2/RD2 the following sequence must be exercised:
Step 1: Activate the combination of control signals.
Step 2: Input the valid address on the address lines.
Step 3: Input the appropriate data on the data lines.
Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
Step 5: Pulse ALE/PROG once.
Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 19.).
8.3.4. Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C51RB2/RC2/RD2.
P 2.7 is used to enable data output.
To verify the TS87C51RB2/RC2/RD2 code the following sequence must be exercised:
Step 1: Activate the combination of program and control signals.
Step 2: Input the valid address on the address lines.
Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 19.)
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
code array is well encrypted.
+5V
VCC
P0.0-P0.7
P1.0-P1.7
P2.0-P2.5
P3.4-P3.5
VSS
GND
D0-D7
A0-A7
A8-A15
RST
PSEN
P2.6
P2.7
P3.3
P3.6
EA/VPP
ALE/PROG
P3.7
XTAL1
4 to 6 MHz
CONTROL
SIGNALS*
PROGRAM
SIGNALS*
* See Table 31. for proper value on these inputs
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