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TS809/810/809R/810R
3-6
2004/09 rev. D
Application Note
Function Description
A microprocessor’s (μP’s) reset input starts the μP
In a know state. The TS809/810/809R/810R assert
reset to prevent code-execution errors during power-up,
power-down, or brownout conditions. They assert a
reset signal whenever the Vcc supply voltage declines
below a preset threshold, keeping it asserted for at
least 140ms after Vcc has risen above the reset
threshold. The TS809/810/809R/810R have a push-pull
output stage.
Applications Information
Negative-Going VCC transients in addition to issuing a
reset to the μP during power-up, power-down, and
brownout conditions, the TS809/810/809R/810R are
relatively immune to short-duration negative-going Vcc
transients (glitches).
The TS809/810/809R/810R do not generate a reset
pulse. The graph was generated using a negative going
pulse applied to Vcc, starting 0.5V above the actual
reset threshold and ending below it by the magnitude
indicated (reset comparator overdrive). The graph
indicates the maximum pulse width a negative going
Vcc transient can have without causing a reset pulse.
As the magnitude of the transient increases (goes
farther below the reset threshold), the maximum
allowable pulse width decreases. Typically, a Vcc
transient that goes 100mV below the reset threshold
and lasts 20μS or less will not cause a reset pulse. A
0.1μF bypass capacitor mounted as close as possible
to the Vcc pin provides additional transient immunity.
Applications Circuit
Ensuring a Valid Reset Output
Down to Vcc=0
When Vcc falls below 1V, the TS809/810/809R/810R
RESET output no longer sinks current - it becomes an
open circuit. Therefore, high impedance CMOS logic
input connected to RESET can drift to undetermined
voltages.
This present no problem in most applications since
most μP and other circuitry is inoperative with Vcc
below 1V.However, in applications where RESET must
be valid down to 0V, adding a pull down resistor to
RESET causes and stray leakage currents to flow to
ground, holding RESET low (Figure 2.) R1’s value is
not critical; 100K is large enough not to load RESET
and small enough to pull RESET to ground. For the
TS809/810/809R/810R if RESET is required to remain
valid for Vcc<1V.
Benefits of Highly Accurate
Reset Threshold
Most μP supervisor ICs have reset threshold voltages
between 5% and 10% below the value of nominal
supply voltages. This ensures a reset will not occur
within 5% of the nominal supply, but will occur when
the supply is 10% below nominal. When using ICs
rated at only the nominal supply ±5%, this leaves a
zone of uncertainty where the supply is between 5%
and 10% low, and where the reset many or may not be
asserted.
Timing Diagram