參數資料
型號： TS68EN360MR25L
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-bitQuad Integrated Communication Controller
中文描述： 32-BIT, 25 MHz, RISC PROCESSOR, CPGA241
封裝： CERAMIC, PGA-241
文件頁數： 43/82頁
文件大小： 874K
代理商： TS68EN360MR25L
43
TS68EN360
2113A–HIREL–03/02
Notes:
1. Transferattributessignals=SIZx,TTx,TMx,R/WandLOCK.
2. TEA/TAshouldnotbeassertedonaDRAMburstaccess,oronthesameclockorbeforeRASx/CSxisasserted.
3. TheclockreferenceisEXTAL,notCLK01.
040BusTypeSRAM/DRAMCyclesACElectricalSpecifications
GND=0Vdc,T
C
=-55to+125
°
C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure34toFigure38).
Number
Characteristic
25.0MHz
33.34MHz
Unit
Min
Max
Min
Max
280
AddressValidtoBADD2-3Valid
-
20
-
15
ns
280A
BADD2-3ValidtoCASAssertion
15
-
10
-
ns
281
AddressInvalidtoBADD2-3Invalid
0
-
0
-
ns
282
ClockHightoCSx/RASxLow(TSS40=0)
4
16
4
12
ns
283
ClockHightoCSx/RASxHigh(CSNT40=0)
4
16
4
12
ns
284
ClockHightoBRKLow
-
20
-
15
ns
284A
ClockLowtoBRKLow
-
20
-
15
ns
285
ClockhightoBRKHigh
-
20
-
15
ns
286
ClockLowtoCSx/RASxLow(TSS40=1)
4
16
4
12
ns
287
ClockLowtoCSx/RASxHigh(CSNT40=1)
4
16
4
12
ns
288
(1)
AddressTransferAttributesValidtoClockHigh(TSS40=0)
10
-
10
-
ns
289
(2)
TALowtoClockHigh(ExternalTermination)
11
-
9
-
ns
290
(2)
ClockHightoTAHigh(ExternalTermination)
-
20
-
15
ns
291
ClockHightoOELow(ReadCycles)
-
20
-
15
ns
292
ClockHightoOEHigh(ReadCycles)
-
20
-
15
ns
293
ClockHightoWELow(WriteCycles)
-
20
-
15
ns
294
ClockHightoWEHigh(WriteCycles)
-
20
-
15
ns
295
ClockHightoCASxLow
4
13
4
10
ns
295A
ClockLowtoCASxLow(040BurstReadonly)
4
13
4
10
ns
296
(3)
ClockHightoCASxHigh
4
13
4
10
ns
297
ClockLowtoAMUXLow
3
16
3
12
ns
298
ClockHightoAMUXHigh
3
16
3
12
ns
299
ClockHightoBADD2-3Valid(040BurstCycles)
4
20
4
15
ns
300
(2)
TEALowtoClockHigh
11
-
-
ns
301
(2)
ClockHightoTEAHigh
2
20
2
15
ns
302
Data,ParityValidtoClockHigh(Data,ParitySetup)
7
-
6
-
ns
303
ClockHightoData,ParityInvalid(Data,ParityHold)
7
-
5
-
ns
305
CLKO1High(AfterTSLow)toParityValid
-
20
-
15
ns
306
CLKO1High(AfterTALow)toParityHi-Z
4
20
15
ns
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