參數(shù)資料
型號(hào)： TS68EN360MA33L
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 32-bitQuad Integrated Communication Controller
中文描述： 32-BIT, 33 MHz, RISC PROCESSOR, CQFP240
封裝： CERAMIC, LCC-240
文件頁(yè)數(shù)： 22/82頁(yè)
文件大?。?/td> 874K
代理商： TS68EN360MA33L
22
TS68EN360
2113A–HIREL–03/02
Notes:
1. AllACtimingisshownwithrespectto0.8Vand2.0Vlevelsunlessotherwisenoted.
2. Thisnumbercanbereducedto5nsifstrobeshaveequalloads.
3. Ifmultiplechipselectsareused,theCSxwidthnegated(#15)appliestothetimefromthenegationofaheavilyloadedchip
selecttotheassertionofalightlyloadedchipselect.
4. HoldtimesarespecifiedwithrespecttoDSorCSxonasynchronousreadsandwithrespecttoCLKO1onfasttermination
reads.Theuserisfreetouseeitherholdtimeforfastterminationreads.
5. Iftheasynchronoussetup(#17)requirementsaresatisfied,theDSACKxlowtodatasetuptime(#31)andDSACKxlowto
BERRlowsetuptime(#48)canbeignored.Thedatamustonlysatisfythedata-intoCLKO1lowsetuptime(#27)forthefol-
lowingclockcycle:BERRmustonlysatisfythelateBERRlowtoCLKO1lowsetuptime(#27A)forthefollowingclockcycle.
6. Toensurecoherencyduringeveryoperandtransfer,BGwillnotbeassertedinresponsetoBRuntilaftercyclesofthecur-
rentoperandtransferarecompleteandRMCisnegated.
7. IntheabsenceofDSACKx,BERRisanasynchronousinputusingtheasynchronoussetuptime(#47).
8. Duringinterruptacknowledgecycles,theprocessormayinsertuptotwowaitstatesbetweenstatesS0andS1.
9. SpecsareforSynchronousArbitrationonly.ASTM=1.
10. CSxspecsareforTRLX=0.
11. CSxspecsareforTRLX=1.
12. CSxspecsareforCSNTQ=0.
13. CSxspecsareforCSNTQ=1;orRASxspecsforDRAMaccesses.
14. SpecsarereadcycleswithparitycheckandPBEE=1.
15. SpecsarereadcycleswithparitycheckandPBEE=0,PAREN=1.
16. RASxspecsareforpagemisscase.
17. SpecificationsonlyapplytoCSx/RASxpins.
18. Specificationappliestononfastterminationcycles.Infastterminationcycles,theBERRsignalmustbenegatedby20ns
afternegationofAS,DS.
81
DSIInputHoldTime
t
DSIH
6
-
3.75
-
ns
82
DSCLCSetupTime
t
DSCSU
10
-
7.5
-
ns
83
DSCLCHoldTime
t
DSCH
6
-
3.75
-
ns
84
DSODelayTime
t
DSOD
-
tcyc+2
0
-
tcyc+2
0
ns
85
DSCLKCycle
t
DSCCYC
2
-
2
-
CLKO1
86
CLKO1HightoFreezeAsserted
t
FRZA
0
35
0
26.25
ns
87
CLKO1HightoFreezeNegated
t
FRZN
0
35
0
26.25
ns
88
CLKO1HightoIFETCHHighImpedance
t
IFZ
0
35
0
26.25
ns
89
CLKO1HightoIFETCHValid
t
IF
0
35
0
26.25
ns
90
CLKO1HightoPERRAsserted
t
CHPA
0
20
0
15
ns
91
CLKO1HightoPERRNegated
t
CHPN
0
20
0
15
ns
92
V
CC
Ramp-UpTimeAtPower-OnReset
t
RMIN
5
-
5
-
ns
BusOperationACTimingSpecifications(Continued)
GND=0Vdc,T
C
=-55to+125
°
C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure7toFigure23).
Number
Characteristic
Symbol
25MHz
33.34MHz
Unit
Min
Max
Min
Max
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