參數(shù)資料
型號(hào)： TS68040VR25A
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Third- Generation 32-bit Microprocessor
中文描述： 32-BIT, 25 MHz, MICROPROCESSOR, CPGA179
封裝： CERAMIC, PGA-179
文件頁數(shù)： 11/49頁
文件大?。?/td> 1637K
代理商： TS68040VR25A
11
TS68040
2116A–HIREL–09/02
Output Buffer Mode
The 68040 is capable of resetting to enable for a combination of either large buffers or
small buffers on the outputs of the miscellaneous control signals, data bus, and address
bus/transfer attribute pins. The large buffers offer quicker output times, which allow for
an easier logic design. However, they do so by driving about 11 times as much current
as the small buffers (refer to TS68040 Electrical specifications for current output). The
designer should consider whether the quicker timings present enough advantage to jus-
tify the additional consideration to the individual signal terminations, the die power
consumption, and the required cooling for the device. Since the TS68040 can be pow-
ered-up in one of eight output buffer modes upon reset, the actual maximum power
consumption for TS68040 rated at a particular maximum operating frequency is depen-
dent upon the power up mode. Therefore, the TS68040 is rated at a maximum power
dissipation for either the large buffers or small buffers at a particular frequency (refer to
TS68040 Electrical specifications). This allows the possibility of some of the thermal
management to be controlled upon reset. The following equation provides a rough
method to calculate the maximum power consumption for a chosen output buffer mode:
P
D
= P
DSB
+ (P
DLB
- P
DSB
) · (PINS
LB
/PINS
CLB
)
where:
(1)
P
D
= Max. power dissipation for output buffer mode
selected
P
DSB
= Max. power dissipation for small buffer mode
(all outputs)
P
DLB
= Max. power dissipation for large buffer mode
(all outputs)
PINS
LB
PINS
CLB
= Number of pins capable of the large buffer
mode
= Number of pins large buffer mode
Table 6 shows the simplified relationship on the maximum power dissipation for eight
possible configurations of output buffer modes.
Table 6.
Maximum Power Dissipation for Output Buffer Mode Configurations
Output Configuration
Maximum Power Dissipation
Data Bus
Address Bus and
Transfer Attrib.
Misc. Control
Signals
PD
Small Buffer
Small Buffer
Small Buffer
P
DSB
Small Buffer
Small Buffer
Large Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 13%
Small Buffer
Large Buffer
Small Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 52%
Small Buffer
Large Buffer
Large Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 65%
Large Buffer
Small Buffer
Small Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 35%
Large Buffer
Small Buffer
Large Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 48%
Large Buffer
Large Buffer
Small Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 87%
Large Buffer
Large Buffer
Large Buffer
P
DSB
+ (P
DLB
- P
DSB
) · 100%
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