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參數(shù)資料
| 型號： | TS634ID |
| 廠商： | 意法半導體 |
| 元件分類： | 運動控制電子 |
| 英文描述： | DUAL WIDE BAND OPERATIONAL AMPLIFIER FOR ADSL LINE INTERFACE |
| 中文描述： | 雙寬帶運放的ADSL線路接口 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 126K |
| 代理商： | TS634ID |
TS634
7/9
Component calculation:
Let us consider the equivalent circuit for a single
ended configuration, Figure 4.
Figure 4 :
Single ended equivalent circuit
Let us consider the unloaded system. Assuming
the currents through R1, R2 and R3
as respectively:
1
As Vo° equals Vo without load, the gain in this
case becomes :
The gain, for the loaded system will be (1):
As shown in figure5, this system is an ideal gener-
ator with a synthesized impedance as the internal
impedance of the system. From this, the output
voltage becomes:
with Ro the synthesized impedance and Iout the
output current. On the other hand Vo can be ex-
pressed as:
2
1
2
R
3
By identification of both equations (2) and (3), the
synthesized impedance is, with Rs1=Rs2=Rs:
Unlike the level Vo° required for a passive imped-
ance, Vo° will be smaller than 2Vo in our case. Let
us write Vo°=kVo with k the matching factor vary-
ing between 1 and 2. Assuming that the current
through R3 is negligeable, it comes the following
resistance divider:
RL
After choosing the k factor, Rs will equal to
1/2RL(k-1).
A good impedance matching assumes:
From (4) and (5) it becomes:
By fixing an arbitrary value for R2, (6) gives:
Finally, the values of R2 and R3 allow us to extract
R1 from (1), and it comes:
2
R
3
with GL the required gain.
1/2
R1
R2
R3
+
_
Vi
Vo
Rs1
-1
Vo°
1/2
RL
---------
--------–
andVi
(
)
Vo
+
R
3
)
,
G
Vi
)
------------------------------
1
----------------------------------
2
----------
2
3
------
+
+
1
2
R
3
------
–
=
=
GL
Vi
)
------------------------------------
1
2
--
1
----------------------------------
1
2
----------
2
3
------
+
+
1
2
R
3
------
–
( )
,
=
=
Vo
ViG
(
)
RoIout
(
)
–
=
2
( )
,
Vo
Vi
1
----------------------------------------------
----------
2
------
+
+
1
------
–
---------------------
3
1
2
R
3
------
–
( )
,
–
=
Figure 5 :
Equivalent schematic. Ro is the syn-
thesized impedance
GL (gain for the
loaded system)
R1
R2 (=R4)
R3 (=R5)
Rs
GL is fixed for the application requirements
GL=Vo/Vi=0.5(1+2R2/R1+R2/R3)/(1-R2/R3)
2R2/[2(1-R2/R3)GL-1-R2/R3]
Abritrary fixed
R2/(1-Rs/0.5RL)
0.5RL(k-1)
Ro
1
2
R
3
------
–
----------------
4
( )
,
=
Ro
Vi.Gi
Iout
1/2
RL
Ro
2
Rs
1
+
---------------------------
=
Ro
1
2
--
RL
5
( )
,
=
2
R
3
------
1
RL
---------
6
( )
,
–
=
R
3
RL
1
---------
–
-------------------
=
R
1
2 1
------
–
GL
1
–
2
R
3
------
–
---------------------------------------------------------
7
( )
,
=
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