
1
FEATURES
APPLICATIONS
YFC PACKAGE TERMINAL ASSIGNMENTS
YFC PACKAGE
B
C
D
1
2
3
Bump View
A
B
C
D
3
2
1
Laser Marking View
A
DESCRIPTION/ORDERING INFORMATION
www.ti.com ................................................................................................................................................ SCDS262A – JANUARY 2009 – REVISED AUGUST 2009
0.7-
DUAL SPDT ANALOG SWITCH
WITH NEGATIVE RAIL CAPABILITY AND 1.8-V COMPATIBLE INPUT LOGIC
Negative Signaling Capability: Maximum
ESD Performance Tested Per JESD 22
Swing From –2.75 V to 2.75 V (V+ = 2.75 V)
–
2500-V Human-Body Model
Low ON-State Resistance (0.7 Ω Typ)
(A114-B, Class II)
Excellent ON-State Resistance Matching
–
1000-V Charged-Device Model (C101)
1.8-V Compatible Control Input Threshold
–
200-V Machine Model (A115-A)
Independent of V+
Control Inputs Are 5.5-V Tolerant
Cell Phones
2.25-V to 5.5-V Power Supply (V
+)
PDAs
Low Charge Injection
Portable Instrumentation
Specified Break-Before-Make Switching
Audio Routing
Latch-Up Performance Exceeds 100 mA Per
Portable Media Players
JESD 78, Class II
D
NC1
V+
NC2
C
COM1
GND
COM2
B
NO1
GND
NO2
A
IN1
N.C.(1)
IN2
1
2
3
(1)
N.C. –No internal connection
The TS5A22366 is a dual single-pole double-throw (SPDT) analog switch that is designed to operate from 2.25 V
to 5.5 V. The device features negative signal capability that allows signals below ground to pass through the
switch without distortion.
The break-before-make feature prevents signal distortion during the transferring of a signal from one path to
another. Low ON-state resistance, excellent channel-to-channel ON-state resistance matching, and minimal total
harmonic distortion (THD) performance are ideal for audio applications.
The TS5A22366 is available is a ultra small 1.6 mm × 1.2 mm wafer-chip-scale package (WCSP) (0.4 mm pitch)
and in a 2 mm × 1.5 mm quad flat (QFN) package (0.5 mm pitch).
ORDERING INFORMATION
TA
PACKAGE(1)(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(3)
NanoFree – WCSP (DSBGA)
–40°C to 85°C
Tape and reel
TS5A22366YFCR
3A_
YFC (Pb-free)
(1)
(2)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
(3)
YFC: The actual top-side marking has one additional character to designate the assembly/test site. Pin 1 identifier indicates solder-bump
composition (1 = SnPb, = Pb-free).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.