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參數(shù)資料
| 型號： | TS4851IJT |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 音頻放大器 |
| 英文描述： | MONO 1 W SPEAKER AND STEREO 160 mW HEADSET BTL DRIVERS WITH DIGITAL VOLUME CONTROL |
| 中文描述： | 單聲道1瓦喇叭和立體聲耳機(jī)橋接160毫瓦司機(jī)數(shù)字音量控制 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 1529K |
| 代理商： | TS4851IJT |
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TS4851
Electrical Characteristics
8/26
Table 5: Electrical characteristics at VCC = +3.0V, GND = 0V, Tamb = 25°C (unless otherwise
specified)
Symbol
Parameter
Min.
Typ.
Max.
Unit
I
CC
Supply Current
Output Mode 7, Vin = 0 V,no load
All other output modes, Vin = 0 V,no load
7.5
4.5
10
6.5
mA
I
STANDBY
Standby Current
Output Mode 0
0.1
2
μA
Voo
Output Offset Voltage (differential)
Vin = 0 V
5
50
mV
Vil
“Logic low” input Voltage
0
0.4
V
Vih
“Logic high” input Voltage
1.4
5
V
Po
Output Power
SPKERout, RL = 8
,
THD = 1%, F = 1 kHz
Rout & Lout, RL = 32
,
THD = 0.5%, F = 1 kHz
Total Harmonic Distortion + Noise
Rout & Lout, Po = 20 mW, F = 1 kHz, RL = 32
SPKERout, Po = 300 mW, F = 1 kHz, RL = 8
Rout & Lout, Po = 15 mW, 20 Hz < F < 20 kHz, RL = 32
SPKERout, Po = 250 mW, 20 Hz < F < 20 kHz, RL = 8
Signal To Noise Ratio (A-Weighted)
300
20
340
30
mW
THD + N
0.5
1
0.5
1
%
SNR
86
dB
PSRR
1
Power Supply Rejection Ratio (Output Mode = 2)
2
Vripple = 200 mV Vpp, F = 217 Hz, Input Floating
Vripple = 200 mV Vpp, F = 217 Hz, Input Terminated 10
Digital Gain Range - Rin & Lin
no load
61
62
dB
G
-34.5
-
+12
dB
Digital gain stepsize
1.5
dB
Stepsize error
G
≥
-22.5 dB
G < -22.5 dB
-0.5
-1
+0.5
+1
dB
Phone In Gain, no load
BTL gain from Phone In to SPKERout
BTL gain from Phone In to Rout & Lout
6
0
dB
Zin
Phone In Input Impedance
1
15
20
25
k
Zin
Rin & Lin Input Impedance (All Gain Setting)
1
37.5
50
62.5
k
tes
Enable Stepup Time - ENB
20
ns
teh
Enable Hold Time - ENB
20
ns
tel
Enable Low Time - ENB
30
ns
tds
Data Setup Time- DATA
20
ns
tdh
Data Hold Time - DATA
20
ns
tcs
Clock Setup time - CLK
20
ns
tch
Clock Logic High Time - CLK
50
ns
tcl
Clock Logic Low Time - CLK
50
ns
fclk
Clock Frequency - CLK
DC
10
MHz
1)
All PSRR data limits are guaranted by evaluation desgin test.
2)
Dynamic measurements [20 x log(rms(Vout)/rms(Vripple)]. Vripple is the superimposed sinus signal to Vcc @ F = 217 Hz.
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