參數(shù)資料
型號(hào): TS4851EIJT
廠(chǎng)商: STMICROELECTRONICS
元件分類(lèi): 音頻控制
英文描述: 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PBGA18
封裝: LEAD FREE, FCP-18
文件頁(yè)數(shù): 15/28頁(yè)
文件大小: 1280K
代理商: TS4851EIJT
TS4851
Application Information
22/28
5.3 Low frequency response
In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3dB cut off
frequency.
Zin is the input impedance of the corresponding input:
20k
for Phone In IHF input
50k
for the 3 other inputs
Note: For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off
frequency doesn’t change with gain setting. Note also that 20k
and 50k are typical values and there are
tolerances around these values (see Electrical Characteristics on page 7).
In Figures 39 to 41, you could easily establish the Cin value for a -3dB cut-off frequency required.
5.4 Decoupling of the circuit
Two capacitors are needed to bypass properly the TS4851, a power supply bypass capacitor Cs and a
bias voltage bypass capacitor Cb.
Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power
supply disturbances.
With 1F, you could expect similar THD+N performances like shown in the datasheet.
If Cs is lower than 1F, THD+N increases in high frequency and disturbances on the power supply rail are
less filtered.
To the contrary, if Cs is higher than 1F, those disturbances on the power supply rail are more filtered.
Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with
input grounded in lower frequency:
If Cb is lower than 1F, THD+N increases at lower frequencies and the PSRR worsens upwards.
If Cb is higher than 1F, the benefit on THD+N and PSRR in the lower frequency range is small.
5.5 Startup time
When the TS4851 is controlled to switch from the full standby mode (output mode 0) to another output
mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be
calculated by the following formulas.
Typical startup time = 0.0175 x Cb (s)
Max. startup time = 0.025 x Cb (s)
(Cb is in F in these formulas)
These formulas assume that the Cb voltage is equal to 0V. If the Cb voltage is not equal to 0V, the startup
time will be always lower.
The startup time is the delay between the negative edge of Enable input (see Description of SPI operation
on page 3) and the power ON of the output amplifiers.
Note: When the TS4851 is set in full standby mode, Cb is discharged through an internal switch.. The time to reach 0V
of Cb voltage is about ms.
)
Hz
(
Cin
Zin
2
1
F
CL
π
=
相關(guān)PDF資料
PDF描述
TS4851IJT 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PBGA18
TS487-1IQT 0.108 W, 2 CHANNEL, AUDIO AMPLIFIER, DSO8
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