
TS3V556
5/8
APPLICATION INFORMATION
MONOSTABLEOPERATION
In the monostable mode,the timer functions as a
one-shot. Referring to figure2 the external capaci-
tor is initially held discharged by a transistor inside
the timer.
V
C C
Reset
Trigger
Out
R
C
Control Voltage
0.01 F
1/2
TS3V556
Figure 2
CAPACITORVOLTAGE = 2.0V/div
R = 9.1k , C = 0.01 F , L
t = 0.1 ms / div
INPUT= 2.0V/div
OUTPUTVOLTAGE = 5.0V/div
Figure 3
TYPICAL CHARACTERISTICS
Figure 1 :
Supply Current (each timer)
versus supply voltage
.
CC
SUPPLYVOLTAGE, V
(V)
C
S
(
μ
300
200
100
0
4
8
12
16
The circuittriggerson anegative-going inputsignal
whenthelevel reaches1/3V
CC
. Oncetriggered,the
circuit remains in this state until the set time has
elapsed,even if it is triggered again during this in-
terval. The duration of the output HIGH state is
given by t = 1.1 R x C.
Notice that since the charge rate and the threshold
level of the comparator are both directly propor-
tional to supply voltage, the timing interval is inde-
pendent of supply. Applying a negative pulse
simultaneously to the Reset terminal (pin 4 or 10)
and theTrigger terminal (pin 2 or 8) during the tim-
ing cycle discharges the external capacitor and
causes thecycle tostartover.The timingcyclenow
starts on the positive edge of the reset pulse. Dur-
ing the timethe reset pulse is applied, the output is
driven to its LOW state.
When a negative triggerpulse is applied to thetrig-
ger terminal, the flip-flop is set, releasing the short
circuit acrosstheexternal capacitorand drivingthe
output HIGH. The voltage across the capacitor in-
creases exponentiallywiththetime constant
τ
=Rx
C.
When the voltage across the capacitor equals 2/3
V
CC
, the comparator resets the flip-flop which then
discharges thecapacitorrapidlyand drivesthe out-
put to its LOW state.
Figure 3 shows the actual waveforms generated in
this mode of operation.
When Reset is not used, it should be tied high to
avoid any possible or false triggering.