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參數(shù)資料
| 型號(hào)： | TS(X)PC603EVGU3LL |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | CERAMIC, BGA-255 |
| 文件頁數(shù)： | 20/38頁 |
| 文件大?。?/td> | 632K |
| 代理商： | TS(X)PC603EVGU3LL |
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TSPC603E
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5.2. Instruction set and addressing modes
The following subsections describe the PowerPC instruction set and addressing modes in general.
5.2.1. PowerPC instruction set and addressing modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent among all instruction
types, permitting efficient decoding to occur in parallel with operand accesses. This fixed instruction length and consistent format
greatly simplifies instruction pipelining.
5.2.1.1. PowerPC instruction set
The PowerPC instructions are divided into the following categories :
D Integer instructions - These include computational and logical instructions.
- Integer arithmetic instructions.
- Integer compare instructions.
- Integer logical instructions.
- Integer rotate and shift instructions.
D Floating-point instructions -These include floating-point computational instructions, as well as instructions that affect the
FPSCR.
- Floating-point arithmetic instructions.
- Floating-point multiply/add instructions.
- Floating-point rounding and conversion instructions.
- Floating-point compare instructions.
- Floating-point status and control instructions.
D Load/store instructions - These include integer and floating-point load and store instructions.
- Integer load and store instruction.
- Integer load and store multiple instructions.
- Floating-point load and store.
- Primitives used to construct atomic memory operations (lwarx and stwcx. instructions).
D Flow control instructions - These include branching instructions, condition register logical instructions, trap instructions, and
other instructions that affect the instruction flow.
- Branch and trap instructions.
- Condition register logical instructions.
D Processor control instructions - These instructions are used for synchronizing memory accesses and management of caches,
TLBs, and the segment registers.
- Move to/from SPR instructions.
- Move to/from MSR.
- Synchronize.
- Instruction synchronize.
D Memory control instruction - These instructions provide control of caches, TLBs, and segment registers.
- Supervisor-level cache management instructions.
- User-level cache instructions.
- Segment register manipulation instructions.
- Translation lookaside buffer management instructions.
Note that this grouping of the instructions does not indicate which execution unit executes a particular instruction or group of instruc-
tions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on single-precision (one
word) and double-precision (one double word) floating-point operands. The PowerPC architecture uses instructions that are four
bytes long and word-aligned. It provides for byte, half-word, and word operand loads and stores between memory and a set of 32
GPRs. It also provides for word and double-word operand loads and stores between memory and a set of 32 floating-point registers
(FPRs).
Computational instructions do not modify memory. To use a memory operand in a computation and then modify the same or another
memory location, the memory contents must be loaded into a register, modified, and then written back to the target location with
distinct instructions.
PowerPC processors follow the program flow when they are in the normal execution state. However, the flow of instructions can be
interrupted directly by the execution of an instruction or by an asynchronous event. Either kind of exception may cause one of several
components of the system software to be invoked.
5.2.1.2. Calculating effective addresses
The effective address (EA) is the 32-bit address computed by the processor when executing a memory access or branch instruction
or when fetching the next sequential instruction.
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