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參數(shù)資料
| 型號(hào)： | TRU2500-L |
| 元件分類(lèi)： | 通信、網(wǎng)絡(luò)模塊及開(kāi)發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大小： | 825K |
| 代理商： | TRU2500-L |
Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON
Several parameters may be measured on a clock
recovery device to characterize its response to initial
start up and transient input data bursts. In convention-
al Phase Locked Loop designs an internal VCO func-
tions as a clock source which must be synchronized
by the loop to the input data rate. The time needed to
synchronize the internal clock and provide error free
data retiming after a long period without input data
transitions is the acquisition time. The response time
to shorter time intervals with no data transitions is
sometimes referred to input blanking. A third measure
of the retiming function is the maximum run length of
ones or zeros with no errors.
A clock recovery device will provide error free perfor-
mance up to a specified maximum number of consec-
utive ones or zeros. In a PLL design, synchronization
is lost briefly and errors occur for a short interval until
synchronization is reestablished. As the run length
increases the PLL drifts further from lock and the
error interval becomes longer. Eventually a limit is
reached where the device is starting from a maximum
frequency offset and the recovery time is the acquisi-
tion time. A PLL will output a frequency with consider-
able error with no data input.
Passive filter based clock recovery depends on the
selectivity or Q of the filter along with the gain of
associated amplifiers to build up a clock signal
derived directly from the input data. Evaluation of the
TRU-2500 shows that the clock signal reaches full
amplitude in about 350ns with a random data input.
Further evaluation shows that error free data is avail-
able at the output after a 250ns interval, less than
1000 data transitions. This interval may be shortened
through the use of a preamble. This acquisition time
is three orders of magnitude shorter than a compara-
ble PLL based design. A plot comparing the recovery
time for input blanking is shown in figure 9.
The SAW filter based TRU-2500 also provides a sta-
ble output clock for a comparable time period of at
least 250ns after input data is stopped. 250ns corre-
spond to 625 bit intervals at 2.5Gbit/s. Evaluation
shows the typical TRU-2500 can run error free with
up to 650 zeros or ones imbedded in a 2e13 random
data pattern.
0
200
1000
100
10
1
0.1
400
600
800
1000
1200
TRU-2500
Input Blanking (us)
R
8
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