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參數(shù)資料
| 型號(hào)： | TRF3750IRGPR |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 7/37頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | PLL 頻率合成器 |
| PLL： | 無 |
| 輸入： | 時(shí)鐘 |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 2.4GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（4x4） |
| 包裝： | 帶卷 (TR) |
| 配用： | TRF3750T-1900EVM-ND - TRF3750T-1900EVM TRF3750Q1900EVM-ND - TRF3750Q1900EVM 296-20836-ND - EVALUATION MOD FOR CDCM7005-QFN 296-20835-ND - EVALUATION MOD FOR CDCM7005-BGA 296-20834-ND - EVALUATION MOD FOR CDC7005-QFN |
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TRF3750
SLWS146B MARCH 2004 REVISED AUGUST 2007
www.ti.com
15
FUNCTIONAL DESCRIPTION
REFIN Stage
This input typically comes from an external oscillator and is the reference used to synthesize the desired
frequency on the output of the complete PLL. The equivalent schematic of this section is given in Figure 24.
The output of this section goes to the R divider, so that the desired PFD frequency can be implemented.
R
PD
PDZ
PD
PDZ
Figure 24. REFIN Stage
RFIN Stage
Figure 25 shows the input stage of the TRF3750. This is where the output of the external VCO is fed back to the
synthesizer. The RFIN signal subsequently feeds the prescaler section.
VBIAS
AVDD
RFIN
RFINB
Figure 25. RFIN Stage
Prescaler Stage
This stage divides down the RFIN frequency before the A and B counters. This is a dual-modulus prescaler and the
user can select any of the following settings: 8/9, 16/17, 32/33, and 64/65.
A and B Counter Stage
The TRF3750 includes a 6-bit A counter and a 13-bit B counter that operate on the output of the prescaler. The A
counter can take values from 0 to 63, while the B counter can take values from 3 to 8191. Also, the value for the B
counter has to be greater than or equal to the value for the A counter. These are CMOS devices, and can easily
operate up to 200 MHz. The selection of the prescaler needs to be such that the resultant frequency does not exceed
the rated 200-MHz threshold.
R Divider
The output of the REFIN stage is fed into the R divider stage. The 14-bit R divider allows the input reference frequency
to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to
16,383 are allowed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TRF3750IRGPRG4 | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 High Perf Integer-N PLL Freq Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| TRF3750Q1900EVM | 功能描述:射頻開發(fā)工具 TRF3750Q1900 Eval Mod RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評(píng)估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
| TRF3750Q2100EVM | 制造商:Texas Instruments 功能描述:TRF3750Q2100 EVAL - Bulk |
| TRF3750Q900EVM | 制造商:Texas Instruments 功能描述:TRF3750Q900 EVAL - Bulk |
| TRF3750T-1900EVM | 功能描述:射頻開發(fā)工具 TRF3750T-1900 Eval Mod RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評(píng)估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V |
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