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參數(shù)資料
| 型號： | TQ8223 |
| 英文描述： | ATM/SONET Demultiplexer |
| 中文描述： | ATM機(jī)/ SONET的多路解復(fù)用器 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 210K |
| 代理商： | TQ8223 |
TQ8223
PRELIMINARY DATA SHEET
3
S
P
T
P
Function Description
Data Regeneration
The TQ8223 recovers and regenerates serial 2.48832
Gb/s data received at DIN and NDIN. The data recovery
can be optimized by adjusting the input data re-timing
clock phase at PHADJ. The PHADJ range is 2.5 +/-
0.5V. This corresponds to a centered sampling point
when PHADJ is 2.5V and a -128 pS or +128 pS offset
for 3V and 2V repectively. PHADJ must be externally
supplied. See the figure below.
The regenerated data is then re-synchronized by re-
timing it with the active 2.48832 GHz clock. (Negative
edge triggered sampling is used.)
The regenerated data can be inverted by tying the
DATINV pin to VEE.
Bit Slipper
The TQ8223 can slip a bit on the incoming data stream.
An active low PECL pin, SLIP, causes the TQ8223 to
skip over one incoming data bit. This can be done for
framing purposes.
Timing Generation
The TQ8223 can receive an external 2.48832 GHz
(nominal) reference clock or generate a 2.48832 GHz
clock through an internal VCO. The output of the active
clock can be monitored at HKCOUT which provides a
30mV
pp
output.
Internal Clock VCO and PLL
Figure 8
contains a reference diagram of operation with
the internal clock and PLL. The internal clock is
selected if the CLKSEL is tied to VDD
and the external
LOCK Signal Hysteresis
Clock Freq. Difference
L
HIGH
LOW
488ppm
30ppm
122ppm
2.5V
0pS
2.0V
128pS
3.0V
-128pS
Time
PHADJ
PHADJ Operation
power supply pin, VOSC, is tied to VDD. CLKIN must be
tied to VEE through a 10k
resistor when the internal
clock is used.
The internal PLL is comprised of a NRZ phase detector,
a charge pump, and the internal VCO. This NRZ phase
detector’s phase error signals are integrated by the
Charge Pump block which then provides a VCO tune
voltage at VTUNEO. See Table 5 for loop filter values.
The internal PLL is completed by connecting VTUNEO
to VTUNE. The purpose of the internal PLL is to adjust
the phase of the internal VCO such that the negative
edge of the internal sampling clock is in the center of
the data eye. A phase offset can be added by adjusting
the PHADJ input voltage. A 38.88 MHz PECL
clock
must be provided at HINTCLK to aid PLL acquisition.
The internal PLL provides an active high LOCK signal if
the frequency difference between the internal VCO and
the 38.88 MHz hint clock remains less than 488 ppm. If
the frequency difference becomes greater than 488
ppm then the LOCK signal deasserts low. The LOCK
signal will assert high when the frequency difference is
less then 122 ppm or 30 ppm. This hysteresis set point
is programmable and is determined by PPMSEL. When
PPMSEL is tied to VEE the LOCK set point is 30 ppm,
when PPMSEL is tied to VDD the LOCK set point is 122
ppm.
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