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參數(shù)資料
| 型號： | TQ2059 |
| 廠商： | TriQuint Semiconductor,Inc. |
| 英文描述： | High-Frequency Clock Generator |
| 中文描述： | 高頻時鐘發(fā)生器 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 195K |
| 代理商： | TQ2059 |
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For additional information and latest specifications, see our website:
www.triquint.com
TQ2059
High-Frequency
Clock Generator
Features
Output frequency range:
200 MHz to 350 MHz
One differential PECL output:
600 mV (min) swing
Common-mode voltage:
V
DD
–1.2 V (max),
V
DD
–1.6 V (min)
Period-to-period output jitter:
30 ps peak-to-peak (typ)
120 ps peak-to-peak (max)
Reference clock input:
20 MHz to 35 MHz TTL-level
crystal oscillator
Self-contained loop filter
Optional 200-ohm pull-down
resistors for AC-coupled outputs
+5 V power supply
28-pin J-lead surface-mount
package
Ideal for designs based on DEC
Alpha AXP
processors
Figure 1. Pinout Diagram
TriQuint’s TQ2059 is a high-frequency clock generator. It utilizes a 20 MHz
to 35 MHz TTL input to generate a 200 MHz to 350 MHz PECL output. The
TQ2059 has a completely self-contained Phase-Locked Loop (PLL) running
at 400 MHz to 700 MHz. This stable PLL allows for a low period-to-period
output jitter of 120 ps (max), and enables tight duty-cycle control of 55%to
45% (worst case).
The TQ2059 provides optional 200-ohm on-chip pull-down resistors which
are useful if the output is AC-coupled to the device being driven. In order
to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN),
and pin 23 (PDR1) should be connected to pin 22 (Q).
Various test modes on the chip simplify debug and testing of systems by
slowing the clock output or by bypassing the PLL.
AVDD
Phase
Detector
1
4
3
2
NC
NC
NC
NC
NC
NC
A
G
P
Q
Q
P
E
VDD
NC
GND
NC
NC
TEST1
28
27
26
19
20
21
22
23
24
25
11
10
9
8
7
6
5
16
17
18
13
12
15
14
N
N
G
R
T
N
G
Control
VCO
MUX
÷
2
MUX
÷
10
TEST2
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