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參數(shù)資料
| 型號(hào)： | TPT-MR-04-SCDSF |
| 元件分類： | 光收發(fā) |
| 英文描述： | FIBER OPTIC TRANSCEIVER, 1529-1564nm, 11300Mbps(Tx), 11300Mbps(Rx), PANEL MOUNT, SC/UPC CONNECTOR |
| 封裝： | ROHS COMPLIANT PACKAGE |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 306K |
| 代理商： | TPT-MR-04-SCDSF |
Page 6 of 12
DS-5192 Rev 01 Jan.9, 2009
Preliminary Datasheet
TPT-MR-04-CCDL5A
Table 8 - Transmitter/Receiver Parallel Data/Clock Timing
Parameter
Symbol
Min.
Typical
Max.
Unit
Notes
Transmitter Data/Clock Timing: SERDES Input Timing at SERDES pin
Duty Cycle(TW/TO)
TDC
40
50
60
%
TxPICLK
Rise and Fall time
Tr/Tf
100
300
ps
20 – 80%
Setup time
Ts
300
ps
TxDin
Hold time
Th
300
ps
TxPICLKP
TxDin[0:15]P/N
To
Tw
Th
Ts
Ts: Measuring from the LHS inner data eye to the immediate rising edge of clock pulse
Th: Measuring from the rising edge of clock pulse to the inner RHS of data eye
Receiver Data/Clock Timing: SERDES Output Timing at SERDES pin
Duty Cycle(TW/TO)
TDC
45
55
%
RxPOCLK
Rise and Fall time
Tr/Tf
100
300
ps
20 – 80%
Tcq_min,
-250
250
ps
RxDout
Data/Clock skew
Tcq_max
-250
250
ps
Rx P O CL K P
R x D o u t [0 :1 5 ]P / N
To
Tw
Tc q_ m a x
Tc q_ m i n
Table 9 - Monitor Clock
Parameter
Symbol
Level
Notes
Transmitter
monitor clock
TxMCLKP/N
LVDS
The LVDS TxMCLK is either a 1/16 or 1/64 replica of the
clock used to time the serial data output. The rate of the
TxMCLK is always the same as that of the TxREFCLK
Receiver
monitor clock
RxMCLKP/N
LVDS
The LVDS RxMCLK is a 1/16 or 1/64 replica of the clock
recovered from the incoming data
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