參數(shù)資料
型號(hào)： TPS736XX
廠商： Texas Instruments, Inc.
英文描述： Cap-Free, NMOS, 400mA Low-Dropout Regulator
中文描述： 無(wú)電容，NMOS管，400mA的低壓差穩(wěn)壓器
文件頁(yè)數(shù)： 12/27頁(yè)
文件大?。?/td> 611K
代理商： TPS736XX
www.ti.com
Board Layout Recommendation to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for V
and V
, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Transient Response
The low open-loop output impedance provided by the
NMOS pass element in a voltage follower configur-
ation allows operation without an output capacitor for
many applications. As with any regulator, the addition
of a capacitor (nominal value 1μF) from the output pin
to ground will reduce undershoot magnitude but
increase duration. In the adjustable version, the
addition of a capacitor, C
FB
, from the output to the
adjust pin will also improve the transient response.
Internal Current Limit
The TPS736xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
V
drops below 0.5V. See
Figure 11
in the Typical
Characteristics section for a graph of I
OUT
vs V
OUT
.
Shutdown
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. V
EN
below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown capa-
bility is not required, the Enable pin can be connected
to V
IN
. When a pull-up resistor is used, and operation
down to 1.8V is required, use pull-up resistor values
below 50k
.
(Fixed Voltage Version)
dV dt
V
OUT
80k
C
OUT
R
LOAD
(4)
Dropout Voltage
The TPS736xx uses an NMOS pass transistor to
achieve extremely low dropout. When (V
IN
- V
OUT
) is
less than the dropout voltage (V
DO
), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the R
DS-ON
of the NMOS
pass element.
(Adjustable Voltage Version)
dV
dt
V
OUT
(R
1
C
OUT
80k
R
2
) R
LOAD
(5)
TPS736xx
SBVS038K–SEPTEMBER 2003–REVISED SEPTEMBER 2005
This noise reduction effect is shown as RMS Noise
Voltage vs C
NR
in the Typical Characteristics section.
The TPS73601 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, C
, from the output to the FB
pin will reduce output noise and improve load transi-
ent performance.
For large step changes in load current, the TPS736xx
requires a larger voltage drop from V
to V
to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of V
- V
OUT
above this line
insure normal transient response.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available head-
room (V
IN
to V
OUT
voltage drop). Under worst-case
conditions [full-scale instantaneous load change with
(V
- V
) close to dc dropout levels], the TPS736xx
can take a couple of hundred microseconds to return
to the specified regulation accuracy.
The TPS736xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above V
OUT
. The
charge pump generates ~250μV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
values of I
OUT
and C
OUT
.
The TPS736xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as alter-
nate power supplies, to the output. This also results
in an output overshoot of several percent if load
current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor C
OUT
and the internal/external load resist-
ance. The rate of decay is given by:
12
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