參數(shù)資料
型號: TPS7348QPW
廠商: Texas Instruments, Inc.
元件分類: 基準電壓源/電流源
英文描述: LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
中文描述: 低技術(shù),集成延遲復(fù)位功能降穩(wěn)壓器
文件頁數(shù): 19/43頁
文件大?。?/td> 638K
代理商: TPS7348QPW
TPS7301Q, TPS7325Q, TPS7330Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124F – JUNE 1995 – REVISED JANUARY 1999
19
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TPS7350Y electrical characteristics at I
O
= 10 mA, V
I
= 6 V, EN = 0 V, C
o
= 4.7
μ
F (CSR
= 1
),
T
J
= 25
°
C, SENSE shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output voltage
5
V
IO = 10 mA,
IO = 100 mA,
IO = 500 mA,
(4.88 V – VO)/IO,
IO = 500 mA
VI = 6 V to 10 V,
IO = 5 mA to 500 mA,
IO = 50
μ
A to 500 mA,
VI = 4.88 V
VI = 4.88 V
VI = 4.88 V
VI = 4.88 V,
2.9
6
Dropout voltage
27
35
mV
146
170
Pass-element series resistance
0.27
0.35
Input regulation
50
μ
A
IO
500 mA
6 V
VI
10 V
6 V
VI
10 V
IO = 50
μ
A
IO = 500 mA
4
25
mV
Output regulation
28
75
mV
41
mV
Ripple rejection
f = 120 Hz
53
dB
51
Output noise-spectral density
f = 120 Hz
2
μ
V/
Hz
Co = 4.7
μ
F
Co = 10
μ
F
Co = 100
μ
F
430
Output noise voltage
10 Hz
f
100 kHz
345
μ
Vrms
220
RESET hysteresis voltage
28
mV
RESET output low voltage
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to Co.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
IO(RESET) = –1.2 mA,
VI = 4.25 V
0.15
0.4
V
相關(guān)PDF資料
PDF描述
TPS7330QPW LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7350QPW LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7301Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7330Q LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
TPS7330Y LOW-DROPOUT VOLTAGE REGULATORS WITH INTEGRATED DELAYED RESET FUNCTION
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