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參數(shù)資料
| 型號： | TPS732XX |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection |
| 中文描述： | 無電容，NMOS管，150mA的低壓差穩(wěn)壓器的反向電流保護(hù) |
| 文件頁數(shù)： | 12/23頁 |
| 文件大小： | 663K |
| 代理商： | TPS732XX |
www.ti.com
DROPOUT VOLTAGE
The TPS732xx uses an NMOS pass transistor to
achieve extremely low dropout. When (V
IN
- V
OUT
) is
less than the dropout voltage (V
DO
), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the R
DS-ON
of the NMOS
pass element.
V
N
( V
RMS
)
8.5
V
RMS
V
V
OUT
(V)
(3)
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE
PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended
that the PCB be designed with separate ground
planes for V
IN
and V
OUT
, with each ground plane
connected only at the GND pin of the device. In
addition, the ground connection for the bypass
capacitor should connect directly to the GND pin of
the device.
TRANSIENT RESPONSE
The low open-loop output impedance provided by the
NMOS
pass
element
configuration allows operation without an output
capacitor
for
many
applications.
regulator, the addition of a capacitor (nominal value
1μF) from the output pin to ground will reduce
undershoot magnitude but increase duration. In the
adjustable version, the addition of a capacitor, C
FB
,
from the output to the adjust pin will also improve the
transient response.
INTERNAL CURRENT LIMIT
The TPS732xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
V
OUT
drops below 0.5V. See
Figure 11
in the Typical
Characteristics section for a graph of I
OUT
vs V
OUT
.
SHUTDOWN
The Enable pin is active high and is compatible with
standard TTL-CMOS levels. V
EN
below 0.5V (max)
turns the regulator off and drops the ground pin
current to approximately 10nA. When shutdown
capability is not required, the Enable pin can be
connected to V
IN
. When a pull-up resistor is used,
and operation down to 1.8V is required, use pull-up
resistor values below 50 k
.
dV dt
V
OUT
80k
C
OUT
R
LOAD
(4)
TPS732xx
SBVS037I–AUGUST 2003–REVISED MAY 2006
for C
NR
= 10nF.
This noise reduction effect is shown as
RMS Noise
Voltage vs C
NR
in the Typical Characteristics section.
The TPS73201 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, C
FB
, from the output to the FB
pin will reduce output noise and improve load
transient performance.
For
TPS732xx requires a larger voltage drop from V
IN
to
V
OUT
to avoid degraded transient response. The
boundary
of
this
transient
approximately twice the dc dropout. Values of V
IN
-
V
OUT
above
this
line
response.
large
step
changes
in
load
current,
the
dropout
region
is
The TPS732xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above V
OUT
.
The charge pump generates ~250μV of switching
noise
at
~2MHz;
however,
contribution is negligible at the output of the regulator
for most values of I
OUT
and C
OUT
.
insure
normal
transient
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the
rate of change in load current, and the available
headroom
(V
to
V
worst-case conditions [full-scale instantaneous load
change with (V
IN
- V
OUT
) close to dc dropout levels],
the TPS732xx can take a couple of hundred
microseconds to return to the specified regulation
accuracy.
charge-pump
noise
voltage
drop).
Under
in
a
voltage
follower
As
with
any
The TPS732xx does not have active pull-down when
the output is over-voltage. This allows applications
that
connect
higher
voltage
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
the load current quickly drops to zero when a
capacitor is connected to the output. The duration of
overshoot can be reduced by adding a load resistor.
The overshoot decays at a rate determined by output
capacitor
C
OUT
and
the
resistance. The rate of decay is given by:
sources,
such
as
internal/external
load
(Fixed voltage version)
12
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