參數(shù)資料
型號: TPS73233DCQT
廠商: Texas Instruments, Inc.
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Cap-Free, NMOS, 150mA Low Dropout Regulator with Reverse Current Protection
中文描述: 無電容,NMOS管,150mA的低壓差穩(wěn)壓器的反向電流保護(hù)
文件頁數(shù): 3/18頁
文件大?。?/td> 427K
代理商: TPS73233DCQT
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted
(1)
POWER DISSIPATION RATINGS
(1)
TPS73201, TPS73215, TPS73216
TPS73218, TPS73225, TPS73230
TPS73233, TPS73250
SBVS037F–AUGUST 2003–REVISED SEPTEMBER 2004
TPS732xx
-0.3 to 6.0
-0.3 to 6.0
-0.3 to 5.5
Internally limited
Indefinite
See Dissipation Ratings Table
-55 to +150
-65 to +150
2
500
UNIT
V
V
V
V
IN
range
V
EN
range
V
OUT
range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, T
J
Storage temperature range
ESD rating, HBM
ESD rating, CDM
°
C
°
C
kV
V
(1)
Stresses beyond those listedunder
absolute maximum ratings
may cause permanent damage to the device. These are stress ratings
only, andfunctional operation of the device at these or any other conditions beyondthose indicated under the Electrical Characteristics is
not implied. Exposureto absolute maximum rated conditions for extended periods may affect devicereliability.
DERATING FACTOR
ABOVE T
A
= 25
°
C
3.9mW/
°
C
5.6mW/
°
C
18.9mW/
°
C
T
25
°
C
POWER RATING
390mW
560mW
1.89W
T
= 70
°
C
POWER RATING
215mW
310mW
1.04W
T
= 85
°
C
POWER RATING
155mW
225mW
0.76W
BOARD
PACKAGE
R
Θ
JC
R
Θ
JA
Low-K
(2)
High-K
(3)
Low-K
(2)
DBV
DBV
DCQ
64
°
C/W
64
°
C/W
15
°
C/W
255
°
C/W
180
°
C/W
53
°
C/W
(1)
(2)
See
Power Dissipation
in the
Applications
section formore information related to thermal design.
The JEDEC Low-K (1s) boarddesign used to derive this data was a 3 inch x 3 inch, two-layer board with2-ounce copper traces on top of
the board.
The JEDEC High-K (2s2p)board design used to derive this data was a 3 inch x 3 inch, multilayer boardwith 1-ounce internal power and
ground planes and 2-ounce copper traces on thetop and bottom of the board.
(3)
3
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