參數(shù)資料
型號(hào): TPS71H33QPWP
廠商: Texas Instruments, Inc.
元件分類(lèi): 基準(zhǔn)電壓源/電流源
英文描述: LOW-DROPOUT VOLTAGE REGULATORS
中文描述: 低壓差電壓調(diào)節(jié)器
文件頁(yè)數(shù): 9/40頁(yè)
文件大小: 634K
代理商: TPS71H33QPWP
TPS71H01Q, TPS71H33Q, TPS71H48Q, TPS71H50Q
LOW-DROPOUT VOLTAGE REGULATORS
SLVS152B
NOVEMBER 1996
REVISED AUGUST 2002
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TPS71H48 electrical characteristics at I
O
= 10 mA, V
I
= 5.85 V, EN = 0 V, C
O
= 4.7
μ
F/CSR
= 1
,
SENSE shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TJ
TPS71H48Q
TYP
4.85
UNIT
MIN
MAX
Output voltage
VI = 5.85 V,
5.85 V
VI
10 V,
IO = 10 mA
5 mA
IO
500 mA
25
°
C
V
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
40
°
C to 125
°
C
25
°
C
25
°
C
25
°
C
25
°
C
4.75
4.95
IO = 10 mA,
VI = 4.75 V
4 75 V
2.9
6
8
Dropout voltage
IO = 100 mA,
VI = 4.75 V
4 75 V
30
37
mV
54
IO = 500 mA,
VI = 4.75 V
4 75 V
150
180
250
Pass-element series
Pass element series
resistance
(4.75 V VO)/IO,
IO = 500 mA
VI = 4.75 V,
0.32
0.35
0.52
Input regulation
VI = 5.85 V to 10 V,
5 85 V to 10 V
50 A
A
IO
500 mA
27
mV
37
IO = 5 mA to 500 mA,
5 85 V
5.85 V
VI
10 V
12
42
mV
Output regulation
80
IO = 50 A to 500 mA
μ
A to 500 mA,
5 85 V
5.85 V
VI
10 V
42
60
mV
130
IO = 50 A
μ
A
42
53
Ripple rejection
f = 120 Hz
39
dB
IO = 500 mA
39
50
35
Output noise-spectral density
f = 120 Hz
2
μ
V/
Hz
CO = 4.7
μ
F
CO = 10
μ
F
CO = 100
μ
F
410
Output noise voltage
10 Hz
f
100 kHz,
328
Vrms
μ
CSR
= 1
212
PG trip-threshold voltage
VO voltage decreasing from above VPG
40
°
C to 125
°
C
4.5
4.7
V
PG hysteresis voltage
25
°
C
50
mV
PG output low voltage
IPG = 1.2 mA,
1 2 mA
VI = 4.12 V
4 12 V
25
°
C
0.2
0.4
V
40
°
C to 125
°
C
0.4
CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must
be taken into account separately.
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