參數(shù)資料
型號(hào)： TPS6734IP
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： 1.5 A SWITCHING REGULATOR, 170 kHz SWITCHING FREQ-MAX, PDIP8
封裝： ROHS COMPLIANT, PLASTIC, DIP-8
文件頁(yè)數(shù)： 17/22頁(yè)
文件大?。?/td> 479K
代理商： TPS6734IP
TPS6734I
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127A – AUGUST 1995 – REVISED JANUARY 1999
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
detailed description
The following descriptions refer to the functional block diagram.
reference
The internal 1.22-V reference is brought out on REF and can source 100
A maximum to external loads. A
0.01-
F to 0.1-F decoupling capacitor connected between REF and GND is recommended to minimize noise
pickup.
oscillator and ramp generator
The oscillator circuit provides a 170-kHz clock, to set the converter operating frequency, and a timing ramp for
slope compensation. The clock waveform is a pulse, a few hundred nanoseconds in duration, that is used to
limit the maximum power-switch duty cycle to 95%. The timing ramp is summed with the current-sense signal
at the input to the current-sense amplifier.
driver latch
The latch, which consists of a set/reset flip-flop and associated logic, is used to control the state of the power
switch by turning the driver on and off. A high output from the latch turns the switch on; a low output from the
latch turns it off. In normal operation, the flip-flop is set high during the clock pulse, but gating keeps the latch
output low until the clock pulse is over. The latch is reset when the PWM comparator output goes high.
current-sense amplifier
The current-sense amplifier has a fixed gain of 6. It amplifies the slope-compensated current-sense voltage (a
summation of the voltage on the current-sense resistor and the oscillator ramp) and feeds it to the PWM
comparator.
error amplifier
The error amplifier is a high-gain differential amplifier used to regulate the converter output voltage. The
amplifier generates an error signal, which is fed to the PWM comparator. The error signal is generated when
a sample of the output voltage is compared to the internal reference and the difference is amplified. The output
sample is obtained from a resistive divider connected between FB and GND. FB is externally connected to the
converter output, and the divider output is connected to both the error amplifier input and COMP. A 0.001-
F
capacitor connected between FB and COMP stabilizes the voltage control loop.
PWM comparator
The PWM comparator resets the drive latch and turns off the power switch whenever the slope-compensated
current-sense signal from the current-sense amplifier exceeds the error signal.
power switch
The power switch is a 0.7-
n-channel MOSFET with current-sensing. The drain is connected to OUT and the
current sense is connected to a resistor. The voltage across the resistor is proportional to the current in the
power switch and is tied to the overcurrent comparator and the current-sense amplifier. In normal operation,
the power switch is turned on at the start of each clock cycle and turned off when the PWM comparator resets
the drive latch.
SS clamp
The SS (soft-start) clamp circuit limits the signal level on error-amplifier output during start-up. The voltage on
SS is amplified and used to momentarily override the error-amplifier output until it rises above that output, at
which point the error-amplifier takes over. This prevents the input to the PWM comparator from exceeding its
common-mode range (the error-amplifier output too high to be reached by the current ramp) by limiting the
maximum voltage on the error-amplifier output during start-up.
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