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參數(shù)資料
| 型號： | TPS65182BRGZT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PQCC48 |
| 封裝： | 7 X 7 MM, 0.9 MM, PLASTIC, QFP-48 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 865K |
| 代理商： | TPS65182BRGZT |
SLAVE ADDRESS
R A
DATA 0
A
S
From master to slave
From slave to master
S
A
P
Start
Acknowlege
Stop
R Read
P
S
1-7
8
9
1-7
8
9
1-7
8
9
P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/
nACK
STOP
START
SDA
SCL
tf
tHD;STA
tLOW
tr
tHD;DAT
tSU;DAT
tHIGH
tSU;STA
tHD;STA
tSP
tSU;STO
tr
tBUF
tf
S
Sr
S
P
SDA
SCL
www.ti.com
SLVSAA2C – MARCH 2010 – REVISED OCTOBER 2010
Figure 4. Subaddress in I2C Transmission
The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established
using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is
sourced from the controller in all cases where the serial data line is bi-directional for data communication
between the controller and the slave terminals. Each device has an open Drain output to transmit data on the
serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high
during data transmission.
Data transmission is initiated with a start bit from the controller as shown in Figure 5. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device will receive serial data on the SDA input and check for valid address and
control information. If the appropriate group and address bits are set for the device, then the device will issue an
acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as
per the Register Map section of this document. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address,
sub-address and data words. Reference Figure 5.
Figure 5. I2C Start/Stop/Acknowledge Protocol
Figure 6. I2C Data Transmission Timing
Copyright 2010, Texas Instruments Incorporated
15
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