參數(shù)資料
型號: TPS65170RHDT
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 4.2 A SWITCHING REGULATOR, 900 kHz SWITCHING FREQ-MAX, PQCC28
封裝: 5 X 5 MM, GREEN, PLASTIC, QFN-28
文件頁數(shù): 20/35頁
文件大小: 4698K
代理商: TPS65170RHDT
RST
REF
RST
C
V
t
=
I
CRST
TPS65170
ENABLE
10k
V
IN
V
LOGIC
V
>V
LOGIC
PG
V
>V
IN
UVLO
V
GL
V
GH
t
DLY
V
S
ENABLE
RST
www.ti.com
SLVSA27 – OCTOBER 2009
Reset pulse timing starts when the buck converter's internal power good signal is asserted and its duration is set
by the size of the capacitor connected between the CRST pin and AGND, as described by Equation 30.
(30)
The duration of the reset pulse also affects power supply sequencing, as the boost converter and positive charge
pump are not enabled until the reset pulse is finished. In applications that do not require a reset signal the
RSTpin can be left floating or tied to AGND. This will not prevent boost converter or positive charge pump from
starting.
If the CRST pin is left open circuit, the duration of the reset pulse will be close to zero (determined only by the
parasitic capacitance present), and the boost converter and positive charge pump will start up instantaneously.
Alternatively, the CRST pin can also be used to enable the boost converter and charge pumps by connecting an
3.3V logic level ENABLE signal via a 10k
Ω resistor, as shown in Figure 34. Using this scheme, the buck
converter starts as soon as VIN exceeds the UVLO threshold, but the negative charge pump is not enabled until
ENABLE goes high. RST also remains low until ENABLE goes high. The boost regulator and positive charge
pump enabled tDLY seconds after ENABLE goes high, where tDLY is defined by the capacitor connected to the
DLY pin. The resulting power supply sequencing is shown in Figure 35.
Figure 34. Using an ENABLE Signal to Control Boost Converter and Charge Pumps
Figure 35. Power Supply Sequencing Using an Enable Signal
Copyright 2009, Texas Instruments Incorporated
27
Product Folder Link(s) :TPS65170
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