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參數(shù)資料
| 型號： | TPS62102EVM |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | TPS62102 Low-Power High-Efficiency Buck Converter Evaluation Module(低功耗，高效率降壓轉(zhuǎn)換器TPS62102評估模塊) |
| 中文描述： | TPS62102低功耗高效率降壓轉(zhuǎn)換器評估模塊（低功耗，高效率降壓轉(zhuǎn)換器TPS62102評估模塊） |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 125K |
| 代理商： | TPS62102EVM |
SLUU070
3
Using the TPS62102 Low-Power High-Efficiency Buck Converter Evaluation Module
This evaluation module allows user control over the SD/SYNC and MODE pins of the TPS62102. As sup-
plied, the MODE (CB1) pin should be left floating. This allows the TPS62102 to automatically determine
whether it operates in the continuous frequency mode or in a pulsed frequency modulation (PFM) mode of
operation. See the TPS62102 data sheet for details
[1]
.
The SD/SYNC pin is jumpered to ground by default. This allows the TPS62102 to free run. Do not allow
this pin to float, as it causes erratic and unpredictable behavior. To synchronize the converter to an exter-
nal source, connect the source to the middle pin of CB2. The source should pulse its output at a frequency
higher than the free running frequency of the converter. Attempting to synchronize to a lower frequency
than this results in erratic behavior. The pulse amplitude should be between 2 V and the VIN supplied to
the evaluation module. Do not use a pulse amplitude higher than VIN. Minimum pulse width for syncro-
nous signals is 50 ns. This pin can also cause the converter to shut down and enter a low-current mode of
operation. To do this, pull the SD/SYNC pin to 2 V or more, and hold it there as long as shutdown is desi-
red. Shutdown occurs approximately 20
μ
s after SD/SYNC is brought high.
UDG
–
00060
f – Frequency – Hz
G
0
100
0
100
P
Gain
Phase
0
100
100M
10k
1M
Figure 2. Gain/Phase Response for the Internal Error Amplifier
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