參數(shù)資料
型號: TPS62050DGSG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 1.4 A SWITCHING REGULATOR, 1000 kHz SWITCHING FREQ-MAX, PDSO10
封裝: GREEN, PLASTIC, MSOP-10
文件頁數(shù): 21/25頁
文件大?。?/td> 602K
代理商: TPS62050DGSG4
www.ti.com
1
2
3
4
5
10
9
8
7
6
VIN
LBO
GND
PG
FB
PGND
SW
EN
SYNC
LBI
DGS PACKAGE
(TOP VIEW)
TPS62050, TPS62051
TPS62052, TPS62054, TPS62056
SLVS432D – SEPTEMBER 2002 – REVISED OCTOBER 2003
PIN ASSIGNMENTS
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
EN
8
I
Enable. A logic high enables the converter, logic low forces the device into shutdown mode, reducing the supply
current to less than 2 A.
FB
5
I
Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider is
connected to this pin. The internal voltage divider is disabled for the adjustable version.
GND
3
I
Ground
LBO
2
O
Open drain low battery output. Logic low signal indicates a low battery voltage.
LBI
6
I
Low battery input
PG
4
O
Power good comparator output. This is an open-drain output. A pullup resistor should be connected between PG
and VOUT. The output goes active high when the output voltage is greater than 95% of the nominal value.
PGND
10
I
Power ground. Connect all power grounds to this pin.
SW
9
O
Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal power
MOSFETS.
SYNC
7
I
Input for synchronization to the external clock signal. This input can be connected to an external clock or pulled to
GND or VI. When an external clock signal is applied, the device synchronizes to this external clock and the device
operates in fixed PWM mode. When the pin is pulled to either GND or VI, the internal oscillator is used and the
logic level determines if the device operates in fixed PWM or PWM/PFM mode.SYNC = HIGH: Low-noise mode
enabled, fixed frequency PWM operation is forcedSYNC = LOW (GND): Power-save mode enabled, PFM/PWM
mode enabled.
VIN
1
I
Supply voltage input
5
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