參數(shù)資料
型號(hào): TPS60110EVM
廠商: Texas Instruments, Inc.
英文描述: TPS60110 DC/DC Converter Evaluation Module(TPS60110 DC/DC轉(zhuǎn)換器的評(píng)估模塊)
中文描述: TPS60110的DC / DC轉(zhuǎn)換器評(píng)估板(TPS60110的DC / DC轉(zhuǎn)換器的評(píng)估模塊)
文件頁(yè)數(shù): 8/10頁(yè)
文件大小: 52K
代理商: TPS60110EVM
Layout of the EVM
1-4
TPS60100 and TPS60110 EVM
(see Table 1–2). Each connector has the supply (In) signal at the first pin, the
logic input at the second pin, and the ground (GND) signal at the third pin. So
it is possible to use jumpers to connect the pin either to input (supply voltage)
or to ground. It is also possible to connect any other signal by using an external
signal source and connecting it to the second pin. These five pins are logic lev-
el CMOS inputs; for the specification of the levels, refer to the datasheets. The
value of the signal connected to the logic pins can be higher than the supply
voltage, but do not exceed the maximum ratings (see datasheets).
Leaving the second pin of these five three-pin connectors open s not allowed
either connect it via a jumper to the first or third pin, or use an appropriate exter-
nal signal source with the appropriate signal level.
Table 1–2.Selected Modes by Connecting the Jumpers
Name
Connected to GND (Pin 3)
3V8
3.3 V at the output
(TPS60110: internal clock is used)
Com
Push-pull mode
EN
Device is disabled
Skip
Fixed-frequency mode
Sync
Device is internally synchronized
Connected to In (Pin 1)
3.8 V at the output
(TPS60110: Do not connect to IN)
Single-ended mode
Device is enabled
Pulse-skip mode
Device is externally synchronized, connect the external
clock to the second pin of connector 3V8.
1.3
Layout of the EVM
Figure 1–2 and Figure 1–3 show the placement of the components and the lay-
out of the EVM. Components are placed only on the top layer of the board. The
signal on the bottom is the ground signal (GND). For good performance, the
entire bottom layer is one GND plane, only interrupted by some vias.
Figure 1–2.Placement of the Components
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