參數(shù)資料
型號： TPS5633CPWPR
元件分類： 基準電壓源/電流源
英文描述： Voltage-Mode SMPS Controller
中文描述： 電壓模式開關電源控制器
文件頁數(shù)： 11/34頁
文件大?。?/td> 811K
代理商： TPS5633CPWPR
TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A
–
MARCH 2000
–
REVISED OCTOBER 2000
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics T
J
= 0
°
to 125
°
C, V
CC
= 2.8 V to 5.5 V (unless otherwise noted) (continued)
output drivers (see Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Duty cycle < 2%,
VBOOT
–
VBOOTLO = 4.5 V,
VHIGHDR = 4 V (sink),
Duty cycle < 2%,
VBOOT
–
VBOOTLO = 4.5 V,
VHIGHDR = 0.5 V (source),
Duty cycle < 2%,
VDRV = 4.5 V,
See Note 2 and Figure 15
tpw < 100 us,
See Note 2 and Figure 15
0.7
2
Peak output current
tpw < 100 us,
See Note 2 and Figure 15
1.2
2
A
tpw < 100
μ
s,
VLOWDR = 4 V (sink),
1.3
2
Duty cycle < 2%,
VDRV = 4.5 V,
See Note 2 and Figure 15
tpw < 100 us,
VLOWDR = 0.5 V (source),
1.4
2
VBOOT
–
VBOOTLO = 4.5 V, VHIGHDR = 0.5 V,
See Note 2
5
Output resistance
VBOOT
–
VBOOTLO = 4.5 V, VHIGHDR = 4 V,
See Note 2
45
VDRV = 4.5 V,
VDRV = 4.5 V,
CL = 3.3 nF,
VBOOTLO=grounded,
CL = 3.3 nF,
INHIBIT grounded,
BOOTLO grounded
VLOWDR = 0.5 V,
VLOWDR = 4 V,
VBOOT= 4.5 V,
See Note 2
9
See Note 2
45
HIGHDR rise/fall time
See Note 2
60
ns
LOWDR rise/fall time
VDRV= 4.5 V,
See Note 2
40
ns
VIN < UVLO, VBOOT=6 V,
10
μ
A
High-side driver quiescent current
INHIBIT connected to +5 V,
f(swx) = 200 kHz,
BOOTLO = 0,
See Note 2
VIN > UVLO
VBOOT = 5.5 V,
CHIGHDR = 50 pF,
2
mA
NOTES:
2. Ensured by design, not production tested.
5. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the Rds(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
LDO N-channel output driver
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Peak output current
VLDODRV = 7.5 V,
VIOSENSE = 0.9
×
VLDOREF,
VLDODRV = 7.5 V,
VIOSENSE = 1.1
×
VLDOREF,
7.5 V
≥
VNGATE
–
LDO
≥
0.5 V,
See Note 2
VN
–
DRV = 3 V (source),
See Note 2
100
μ
A
VN
–
DRV=0 V (sink),
See Note 2
1.5
mA
Open loop voltage gain
(VNGATE
–
LDO / VSENSE
–
LDO)
VIN = 5.5 V,
3000
(70)
V/V
(dB)
Power supply ripple rejection
f = 1 kHz,
5.5 V
≥
VIN
≥
2.55 V,
See Note 2
CO=10
μ
F,
TJ=125
°
C,
60
dB
NOTE 2. Ensured by design, not production tested.
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