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參數(shù)資料
| 型號(hào)： | TPS5625CPWPR |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Voltage-Mode SMPS Controller |
| 中文描述： | 電壓模式開關(guān)電源控制器 |
| 文件頁數(shù)： | 27/34頁 |
| 文件大小： | 811K |
| 代理商： | TPS5625CPWPR |
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TPS56302
DUAL-OUTPUT LOW-INPUT-VOLTAGE
DSP POWER SUPPLY CONTROLLER WITH SEQUENCING
SLVS289A
–
MARCH 2000
–
REVISED OCTOBER 2000
27
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
layout and component value consideration (continued)
5.
When configuring the high-side driver as a boot-strap driver, the connection from BOOTLO to the power
FETs should be as short and as wide as possible. LOSENSE/LOHIB should have a separate connection
to the FETs since BOOTLO will have large peak current flowing through it.
6.
The bulk storage capacitors across V
IN
should be placed close to the power FETs. High-frequency bypass
capacitors should be placed in parallel with the bulk capacitors and connected close to the drain of the
high-side FET and to the source of the low-side FET.
7.
HISENSE and LOSENSE/LOHIB should be connected very close to the drain and source, respectively, of
the high-side FET. HISENSE and LOSENSE/LOHIB should be routed very close to each other to minimize
differential-mode noise coupling to these traces. Ceramic decoupling capacitors should be placed close to
where HISENSE connects to V
IN
, to reduce high-frequency noise coupling on HISENSE.
The EVM board (SLVP-139) is used in the test. The test results are shown in the following.
Figure 23
IO
–
Output Current
–
A
EFFICIENCY OF
RIPPLE REGULATOR (3.3 V)
60
40
1
3
80
70
50
2
4
5
100
0
E
–
90
VIN = 5 V
Figure 24
IO
–
Output Current
–
A
RIPPLE REGULATOR
LOAD REGULATION (3.3 V)
–
2
1
3
0
–
1
2
4
5
1
0
2
VIN = 5 V
L
–
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