參數(shù)資料
型號(hào)： TPS54673PWP
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 12 A SWITCHING REGULATOR, 762 kHz SWITCHING FREQ-MAX, PDSO28
封裝： GREEN, PLASTIC, HTSSOP-28
文件頁(yè)數(shù)： 3/21頁(yè)
文件大?。?/td> 570K
代理商： TPS54673PWP
TPS54673
SLVS433A SEPTEMBER 2002 REVISED FEBRUARY 2005
www.ti.com
11
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 6 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Eight vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Top
Side Analog Ground Area
0.3478
0.0150
0.06
0.0256
0.1700
0.1340
0.0630
0.0400
0.0180
4 PL
0.2090
0.0130
8 PL
Minimum Recommended Exposed
Copper Area for Powerpad. 5-mm
Stencils May Require 10 Percent
Larger Area
0.0650
0.0500
0.0650
0.0339
0.0500
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
0.3820
Figure 12. Recommended Land Pattern for 28-Pin PWP PowerPAD
PERFORMANCE GRAPHS
Data shown is for the circuit in Figure 10 with precharge disabled (D1 and D2 removed) except for slow-start timing
of Figure 19. All data is for VI = 3.3 V, VO = 2.5 V, fs = 700 kHz and TA = 25°C, unless otherwise specified.
Figure 13
50
55
60
65
70
75
80
85
90
95
100
0123
4567
VI = 5 V, VO = 2.5 V
Efficiency
%
EFFICIENCY
vs
OUTPUT CURRENT
IO Output Current A
VI = 3.3 V, VO = 2.5 V
Figure 14
2.48
2.485
2.49
2.495
2.5
2.505
2.51
2.515
2.52
01
23
4567
Output
V
oltage
V
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
IO Output Current A
V
O
VI = 3.3 V
VI = 5 V
Figure 15
2.48
2.485
2.49
2.495
2.5
2.505
2.51
2.515
2.52
3
3.5
4
4.5
5
5.5
6
IO = 3 A
VI Input Voltage V
Output
V
oltage
V
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
V
O
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