參數(shù)資料
型號(hào)： TPS54377RHFRG4
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 穩(wěn)壓器
英文描述： 7.5 A SWITCHING REGULATOR, 1600 kHz SWITCHING FREQ-MAX, PQCC24
封裝： 4 X 5 MM, GREEN, PLASTIC, QFN-24
文件頁(yè)數(shù)： 5/22頁(yè)
文件大小： 727K
代理商： TPS54377RHFRG4
www.ti.com
VBIAS Regulator (VBIAS)
Oscillator and PWM Ramp
SWITCHINGFREQUENCY (MHz)=
51k
R( )+4.7k
W
(4)
Voltage Reference
Error Amplifier
PWM Control
SLVS779 – SEPTEMBER 2007
The VBIAS regulator provides internal analog and
The oscillator frequency can be set to internally fixed
digital blocks with a stable supply voltage over
values of 350 kHz or 550 kHz using the SYNC pin as
variations in junction temperature and input voltage. A
a static digital input. If a different frequency of
high quality, low-ESR, ceramic bypass capacitor is
operation is required for the application, the oscillator
required on the VBIAS pin. X7R or X5R grade
frequency can be externally adjusted from 280 kHz to
dielectrics are recommended because their values
1600 kHz by connecting a resistor to the RT pin to
are more stable over temperature. The bypass
ground and floating the SYNC pin. The switching
capacitor should be placed close to the VBIAS pin
frequency is approximated by the following equation,
and returned to AGND. External loading on VBIAS is
where R is the resistance from RT to AGND:
allowed, with the caution that internal circuits require
a minimum VBIAS of 2.70 V, and external loads on
VBIAS with ac or digital switching noise may degrade
External
synchronization
of
the
PWM
ramp
is
performance. The VBIAS pin may be useful as a
possible over the frequency range of 330 kHz to 1600
reference voltage for external circuits.
kHz by driving a synchronization signal into SYNC
and connecting a resistor from RT to AGND. Choose
an RT resistor that sets the free-running frequency to
The voltage reference system produces a precise Vref
80%
of
the
synchronization
signal.
signal by scaling the output of a temperature stable
summarizes the frequency selection configurations.
bandgap circuit. During manufacture, the bandgap
and scaling circuits are trimmed to produce 0.891 V
at the output of the error amplifier, with the amplifier
connected as a voltage follower. The trim procedure
adds
to
the
high
precision
regulation
of
the
TPS54377, since it cancels offset errors in the scale
and error amplifier circuits.
Table 1. Summary of the Frequency Selection Configurations
SWITCHING FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally set
Float or AGND
Float
550 kHz, internally set
≥ 2.5 V
Float
Externally set 280 kHz to 1600 kHz
Float
R = 27.4 k to 180 k
Externally synchronized frequency
Synchronization signal
R = RT value for 80% of external synchronization frequency
The high performance, wide bandwidth, voltage error
to its valley voltage. When the ramp begins to charge
amplifier sets the TPS54377 apart from most dc/dc
back up, the low-side FET turns off and high-side
converters. The user is given the flexibility to use a
FET turns on. As the PWM ramp voltage exceeds the
wide range of output L and C filter components to suit
error amplifier output voltage, the PWM comparator
the particular application needs. Type 2 or type 3
resets the latch, thus turning off the high-side FET
compensation
can
be
employed
using
external
and turning on the low-side FET. The low-side FET
compensation components.
remains on until the next oscillator pulse discharges
the PWM ramp.
During transient conditions, the error amplifier output
Signals from the error amplifier output, oscillator, and
could be below the PWM ramp valley voltage or
current limit circuit are processed by the PWM control
above the PWM peak voltage. If the error amplifier is
logic. Referring to the internal block diagram, the
high, the PWM latch is never reset and the high-side
control logic includes the PWM comparator, OR gate,
FET remains on until the oscillator pulse signals the
PWM latch, and portions of the adaptive dead-time
control logic to turn off the high-side FET and turns
and control logic block. During steady-state operation
on the low-side FET. The device operates at its
below
the
current
limit
threshold,
the
PWM
maximum duty cycle until the output voltage rises to
comparator
output
and
oscillator
pulse
train
the
regulation
set-point,
setting
VSENSE
to
alternately reset and set the PWM latch. Once the
approximately the same voltage as Vref. If the error
PWM latch is set, the low-side FET remains on for a
amplifier output is low, the pwm latch is continually
minimum duration set by the oscillator pulse duration.
reset and the high-side FET does not turn on. The
During this period, the PWM ramp discharges rapidly
Copyright 2007, Texas Instruments Incorporated
13
Product Folder Link(s): TPS54377
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