參數(shù)資料
型號: TPS54357MPWPREP
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 6.5 A SWITCHING REGULATOR, 700 kHz SWITCHING FREQ-MAX, PDSO16
封裝: PLASTIC, HTSSOP-16
文件頁數(shù): 8/35頁
文件大小: 1132K
代理商: TPS54357MPWPREP
LAYOUT INFORMATION
PCB Layout
SLVS684A – JANUARY 2007 – REVISED JULY 2009 ....................................................................................................................................................... www.ti.com
Figure 23. TPS5435x PCB Layout
The VIN pins should be connected together on the printed circuit board (PCB) and bypassed with a low-ESR
ceramic bypass capacitor. Care should be taken to minimize the loop area formed by the bypass capacitor
connections, the VIN pins, and the TPS5435x ground pins. The minimum recommended bypass capacitance is
10-
F ceramic with a X5R or X7R dielectric, and the optimum placement is closest to the VIN pins and the
AGND and PGND pins. See Figure 23 for an example of a board layout. The AGND and PGND pins should be
tied to the PCB ground plane at the pins of the IC. The source of the low-side MOSFET and the anode of the
Schottky diode should be connected directly to the PCB ground plane. The PH pins should be tied together and
routed to the drain of the low-side MOSFET or to the cathode of the external Schottky diode. Since the PH
connection is the switching node, the MOSFET (or diode) should be located very close to the PH pins, and the
area of the PCB conductor minimized to prevent excessive capacitive coupling. The recommended conductor
width from pins 14 and 15 is 0.050 in to 0.075 in of 1-oz copper. The length of the copper land pattern should be
no more than 0.2 in.
For operation at full-rated load, the analog ground plane must provide adequate heat dissipating area. A 3-in ×
3-in plane of copper is recommended, though not mandatory, dependent on ambient temperature and airflow.
Most applications have larger areas of internal ground plane available, and the PowerPAD package should be
connected to the largest area available. Additional areas on the bottom or top layers also help dissipate heat,
and any area available should be used when 3 A or greater operation is desired. Connection from the exposed
area of the PowerPAD package to the analog ground-plane layer should be made using 0.013-in diameter vias to
avoid solder wicking through the vias. Four vias should be in the PowerPAD area, with four additional vias
outside the pad area and underneath the package. Additional vias beyond those recommended to enhance
thermal performance should be included in areas not under the device package.
16
Copyright 2007–2009, Texas Instruments Incorporated
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