參數(shù)資料
型號: TPS54350EVM-235
廠商: Texas Instruments, Inc.
英文描述: 3-Amp SWIFT Regulator Evaulation Module(3A SWIFT穩(wěn)壓器TPS54350的評估模塊)
中文描述: 3安培的SWIFT穩(wěn)壓Evaulation模塊條第(3A SWIFT的穩(wěn)壓器TPS54350的評估模塊)
文件頁數(shù): 12/31頁
文件大?。?/td> 551K
代理商: TPS54350EVM-235
Modifications
1-5
Introduction
Table 14.Internal UVLO Setting
Start Voltage Threshold
Stop Voltage Threshold
VIN
4.4 V
3.7 V
UVLO
1.18 V
1.09 V
To set a different set of thresholds, R6 and R7 can be selected using the
following equations.
Equation 13.
R6
VI(start)
UVLO(start)
R7
R7
Equation 14.
R6
VI(stop)
UVLO(stop)
R7
R7
10 k
is a good value for R7.
1.3.5
Synchronization
The SYNC pin can be configured as an input or as an output, depending on
the configuration of the RT pin. If the RT pin is open or tied to AGND, the SYNC
pin functions as an output. When operating as an output, the signal’s falling
edge is one half of the switching cycle and approximately 180
°
out of phase
with the rising edge of the PH pins. Thus, two TPS54350 devices operating in
a system can share an input capacitor and draw ripple current at twice the
frequency of a single unit.
If the RT pin is programmed with a resistor to AGND, the SYNC pin functions
as an input. When operating as an input, the SYNC pin is a falling-edge
triggered signal, and the resistor at the RT pin should be set to provide a
frequency equal to 90 percent of the SYNC input frequency.
1.3.6
Power Good
An internal circuit monitors the VSENSE input voltage to verify that it is within
a guard band around the reference voltage. If these voltages are close to each
other in value, and no other fault signals are present, the PWRGD pin presents
a high impedance. A low on the PWRGD pin indicates a fault. The PWRGD
pin has been designed to provide a weak pull-down and indicates a fault even
when the device is unpowered. If the TPS54350 has power and has any fault
flag set, the TPS54350 indicates the power is not good by driving the PWRGD
pin low. The following events, singly or in combination, indicates power not
good:
VSENSE pin out of bounds
Overcurrent
Thermal shutdown
UVLO undervoltage
Input voltage not present (weak pull-down)
Slow-starting
VBIAS voltage is low
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