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參數(shù)資料
| 型號： | TPS51120RHBTG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 0.1 A DUAL SWITCHING CONTROLLER, 350 kHz SWITCHING FREQ-MAX, PQCC32 |
| 封裝： | GREEN, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 826K |
| 代理商： | TPS51120RHBTG4 |
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Soft-Stop
Powergood
Current Sensing and Overcurrent Protection
Overvoltage Protection
SLUS670B – JULY 2005 – REVISED FEBRUARY 2007
DETAILED DESCRIPTION (continued)
Discharge mode or ‘Soft Stop’ is always on during Faults or Disable. In this mode, an event that would cause the
switcher to be turned off (EN1 or EN2 low, OVP, UVP, UVLO) causes the output to be discharged through 10-
transistor inside the VO terminal. The external rectifying MOSFET is not turned on for the soft off operation to
avoid a chance to cause negative voltage at the output. Soft-stop time constant is a function of the output
capacitance and the resistance of the discharge transistor. This discharge ensures that, upon restart, the
regulated voltage always starts from zero volts. In case a SMPS is restarted before discharge completion,
soft-stop is terminated and the switching resumes after the reference level comes back to the remaining output
voltage.
The TPS51120 has dedicated powergood output for each SMPS, PGOOD1 and PGOOD2. The PGOOD
monitors are open drain 5-mA pull down outputs. These outputs are low on startup and stay low until the
switcher feedback voltages are within a specified range for 256 clocks or approximately 1 ms. If the VFB pin falls
outside the 10% tolerance band, the respective PGOOD pin goes low within microseconds. Then if the VFB pin
comes back within 5% of target (1 V) for greater than 1 ms, then the respective PGOOD pin goes high again.
The PGOOD pin should be typically pulled up through a 100 k
or greater value resistor to the V5FILT pin. Both
PGOOD pins go low during fault conditions (Thermal Shutdown, UVLO, UVP, OVP) and Disable.
The SMPS has cycle-by-cycle over current limiting. The inductor current is monitored during the rectifying
MOSFET is on and the controller does not allow the next ON cycle while the current level is above the trip
threshold. In order to provide good accuracy and cost effective solution, TPS51120 supports both of external
resistor sensing and MOSFET RDS(on) sensing which are selected by CS terminal connection. For resistor
sensing scheme, an appropriate current sensing resistor should be connected between the source terminal of
the bottom MOSFET and PGND. CS pin is connected to the bottom MOSFET source terminal node. The
inductor current is monitored by the voltage between PGND pin and CS pin. In this scheme, the trip level is fixed
value of 80 mV. For RDS(on) sensing scheme, CS terminal is connected to V5FILT through a trip voltage setting
resistor RTRIP. In this scheme, CS terminal sinks 10-A ITRIP current and the trip level is set to the voltage across
the RTRIP. The trip level should be in the range of 30 mV to 150 mV. This allows designer to select a variety of
MOSFETs for the bottom arm. The inductor current is monitored by the voltage between PGND pin and LL pin
so that LL pin should be connected to the drain terminal of the bottom MOSFET. ITRIP has 4500ppm/°C
temperature slope, with respect to its 25
°C value, to compensate the temperature dependency of the R
DS(on). In
either scheme, PGND is used as the positive current sensing node so that PGND pin should be connected to
the proper current sensing device, i.e. the sense resistor or the source terminal of the bottom MOSFET. In an
overcurrent condition, since the current to the output capacitor is limited while the load drags more, the output
voltage tends to go down. It ends up with passing into the undervoltage protection and latches off as both DRVH
and DRVL are at low level.
Table 3. Current Sensing Connection
Temperature
CS
Threshold
Coefficient (ppm/
°C)
RDS(on) sensing
V5FILT
ITRIP× RTRIP / RDS(on)
4500
RSENSE sensing
Bottom FET source node (=RSENSE (-) node)
80 mV / RSENSE
none
For over voltage protection (OVP), the TPS51120 monitors VFB voltage. When the VFB voltage is higher than
115% of the target, the OVP comparator output goes high and the circuit latches both switchers. The offending
channel is latched DRVH low and DRVL high, the other channel is simply latched as DRVH and DRVL at low.
Be aware negative voltage may appear at the output terminal of the offending channel because of LC resonant
configured by the power inductor and the output capacitor. The system designer is responsible to this negative
voltage if any protection is need. The OVP propagation delay is less than 3
s.
15
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