參數(shù)資料
型號： TPS51117RGYRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 550 kHz SWITCHING FREQ-MAX, PQCC14
封裝： GREEN, PLASTIC, MO-241BA, VQFN-14
文件頁數(shù)： 9/30頁
文件大?。?/td> 926K
代理商： TPS51117RGYRG4
Control
Logic
and
Driver
R1
R2
+
VFB
-
DRVL
IL
VoltageDivider
PWM
VIN
Lx
DRVH
Io
Vc
Co
ESR
RL
Ic
SwitchingModulator
0.75V
+
OutputCapacitor
o +
1
2p
ESR
Co
v
sw
4
R1 +
V
OUT *
0.75
R2
www.ti.com...................................................................................................................................... SLVS631B – DECEMBER 2005 – REVISED SEPTEMBER 2009
APPLICATION INFORMATION
LOOP COMPENSATION AND EXTERNAL PARTS SELECTION
D-CAP Mode Operation
A buck converter system using D-CAP Mode can be simplified as shown in Figure 23.
Figure 23. Simplified Diagram of the Modulator
The VFB voltage is compared with the internal reference voltage after the divider resistors. The PWM comparator
determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep
the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output
voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases.
For loop stability, the 0 dB frequency, f 0, defined in the follow equation must be lower than 1/4 of the switching
frequency.
(6)
As f 0 is determined solely by the output capacitor characteristics, loop stability of D-CAP Mode is determined
by capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100
μF and ESR in range of 10 m. These values make f 0 in the order of 100 kHz or less and the loop is stable.
However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode.
Although D-CAP Mode provides many advantages such as ease-of-use, minimum external component
configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient
feedback signal needs to be provided by an external circuit to reduce the jitter level. The required signal level is
approximately 15 mV at the comparing point. This generates Vripple = (VOUT/0.75) × 15 mV at the output node.
The output capacitor ESR should meet this requirement.
The external component selection is simple in D-CAP Mode:
1. Determine the value of R1 and R2
The recommended R2 value is 10 k
to 100 k. Calculate R1 by Equation 7.
(7)
2. Choose RTON
Copyright 2005–2009, Texas Instruments Incorporated
17
Product Folder Link(s) :TPS51117
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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TPS51117RGYTG4 功能描述:DC/DC 開關(guān)控制器 Wide Vin Synch Buck Cntrlr RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關(guān)頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風(fēng)格: 封裝 / 箱體:CPAK
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