參數(shù)資料
型號(hào)： TPS40132RHBT
廠商： TEXAS INSTRUMENTS INC
元件分類： 穩(wěn)壓器
英文描述： 40 A SWITCHING CONTROLLER, 1200 kHz SWITCHING FREQ-MAX, PQCC32
封裝： GREEN, PLASTIC, QFN-32
文件頁(yè)數(shù)： 39/40頁(yè)
文件大?。?/td> 1032K
代理商： TPS40132RHBT
www.ti.com
SLUS776A – DECEMBER 2007 – REVISED FEBRUARY 2008
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Gate drive output for the high-side N-channel MOSFET switch for PWM2. Output is referenced to SW2 and
HDRV2
25
O
is bootstrapped for enhancement of the high-side switch
Used to set the cycle-by-cycle current limit threshold. If ILIM threshold is reached, the PWM cycle is
terminated and the converter delivers limited current to the output. The relationship between ILIM and the
ILIM
15
I
maximum phase current is described in Equation 2 and Equation 3. See the Overcurrent Protection section
for more details.
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM1. See Layout
LDRV1
29
O
Considerations section.
Gate drive output for the low-side synchronous rectifier (SR) N-channel MOSFET for PWM2. See Layout
LDRV2
27
O
Considerations section.
OVSET
2
I
A resistor divider, on this pin connected to the output voltage sets the overvoltage sense point.
Power good indicator of the output voltage. This open-drain output connects to a voltage via an external
PGOOD
16
O
resistor. When the FB pin voltage is between 93% and 107% of VREF, the PGOOD output is in a high
impedance state.
Power ground reference for the controller lower gate drivers. There should be a high-current return path
PGND
28
-
from the sources of the lower MOSFETs to this pin.
RT
17
I
Connecting a resistor from this pin to ground sets the oscillator frequency.
Provides user programmable soft-start by means of a capacitor connected to the pin. If an undervoltage or
SS
23
I
over current fault is detected the soft-start capacitor cycles 7 times with no switching before a normal
soft-start sequence allowed.
Connect to the switched node on converter 1. Power return for the channel 1 upper gate driver. There
SW1
31
I
should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by
the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction.
Connect to the switched node on converter 2. Power return for the channel 2 upper gate driver. There
SW2
26
I
should be a high-current return path from the source of the upper MOSFET to this pin. It is also used by
the adaptive gate drive circuits to minimize the dead time between upper and lower MOSFET conduction.
UVLO
22
O
A voltage divider from VIN to this pin, set to 1V, determines the input voltage that starts the controller.
Power input for the LDO linear regulator that powers the differential amplifier and the current sense
VDD
12
I
amplifiers.
VOUT
3
I
Non-inverting input of the differential amplifier. This pin should be connected to VOUT at the point of load.
VREF
9
O
Output of an internal reference voltage. The load may be up to 100-
A DC.
VIN5
30
I
Power input for the device. A 1.0-
F ceramic capacitor should be connected from this pin to ground.
8
Copyright 2007–2008, Texas Instruments Incorporated
Product Folder Link(s) :TPS40132
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