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參數(shù)資料
| 型號： | TPS40054PWPRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | GREEN, PLASTIC, HTSSOP-16 |
| 文件頁數(shù)： | 7/35頁 |
| 文件大?。?/td> | 866K |
| 代理商： | TPS40054PWPRG4 |
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( )
3
OC
OS
DS on
max
ILIM
SINK
I
R
V
42.86
10
R
1.12
I
-
é
ù
+
=
+
W
(15)
SYNCHRONIZING TO AN EXTERNAL SUPPLY
(
)
( )
T dummy
6
SYNC
1
R
17
k
f
17.82
10-
÷
=
-
W
÷
è
(16)
(
) (
)
KFF
IN(min)
KFF
T
R
V
58.14
R
1340
=
-
+
W
(17)
LOOP COMPENSATION
A
MOD +
V
IN
V
S
or
A
MOD(dB) + 20
log
V
IN
V
S
(18)
D +
V
O
V
IN
+
V
C
V
S
or
V
O
V
C
+
V
IN
V
S
(19)
www.ti.com ...................................................................................................................................... SLUS593F – DECEMBER 2003 – REVISED SEPTEMBER 2008
The current limit programming resistor (RILIM) is calculated using Equation 15. Care must be taken in choosing
the values used for VOS and ISINK in the equation. In order to ensure the output current at the overcurrent level,
the minimum value of ISINK and the maximum value of VOS must be used.
where
I
SINK is the current into the ILIM pin and is 8.5 A, minimum
I
OC is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current plus
one-half of the peak inductor current
V
OS is the overcurrent comparator offset and is nominally –20 mV, maximum
The TPS4005x can be synchronized to an external clock through the SYNC pin. Synchronization occurs on the
rising edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4005x to freely run at the
frequency programmed by RT.
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, RKFF needs to be adjusted for the higher switching
frequency. In order to specify the correct value for RKFF at the synchronizing frequency, calculate a dummy value
for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in the
design.
Use the value of RT(dummy) to calculate the value for RKFF.
This value of RKFF ensures that UVLO is not engaged when operating at the synchronization frequency.
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x
uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be
included. The modulator gain is described in Figure 11, with VIN being the minimum input voltage required to
cause the ramp excursion to cover the entire switching period as described in Equation 18.
Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the
maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO / VIN. To get the control voltage to
output voltage modulator gain in terms of the input voltage and ramp voltage,
Copyright 2003–2008, Texas Instruments Incorporated
15
Product Folder Link(s): TPS40054 TPS40055 TPS40057
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