參數(shù)資料
型號: TPS40021PWP
廠商: TEXAS INSTRUMENTS INC
元件分類: 穩(wěn)壓器
英文描述: 0.01 A SWITCHING CONTROLLER, 1100 kHz SWITCHING FREQ-MAX, PDSO16
封裝: GREEN, PLASTIC, HTSSOP-16
文件頁數(shù): 6/36頁
文件大?。?/td> 724K
代理商: TPS40021PWP
TPS40020
TPS40021
SLUS535D MARCH 2003 REVISED JULY 2007
www.ti.com
14
APPLICATION INFORMATION
Synchronization
The TPS4002x can be synchronized to an external reference frequency higher than the free running oscillator
frequency. The recommended method is to use a diode and a push pull drive signal as shown in Figure 6.
PREFERRED
UDG03032
ALTERNATE
Minumize
Output/Stray
Capacitance
on ILIM Node
1
2
ILIM/SYNC
VDD
TPS4002XPWP
VDD
1
2
ILIM/SYNC
VDD
TPS4002XPWP
VDD
50 ns to 100 ns
Figure 6. Synchronization Methods
This design allows synchronization up to the maximum operating frequency of 1 MHz. For best results the
nominal operating frequency of a converter that is to be synchronized should be kept as close as practicable
to the synchronization frequency to avoid excessive noise induced pulse width jitter. A good target is to shoot
for the free run frequency to be 80% of the synchronized frequency. This ensures that the synchronization
source is the frequency determining element in the system and not to adversely affect noise immunity.
Other methods of implementing the synchronization function include using an open collector or open drain
output device directly, or discreet devices to pull the ILIM/SYNC pin down. These do work but performance can
suffer at high frequency because the ILIM/SYNC pin must rise to (VDD 1.0 V) before the next switching cycle
begins. Any time that this requires is directly subtracted from the maximum pulse width available and should
be considered when choosing devices to drive ILIM/SYNC. Consequently, the lowest output capacitance
devices work best.
During a synchronization cycle, the current sink on the ILIM/SYNC pin becomes disabled when ILIM/SYNC is
pulled below 1.0 V. The ILIM/SYNC current sink remains disabled until ILIM/SYNC reaches (VDD 1.0 V) This
removes the load on the ILIM/SYNC pin to allow the voltage to slew rapidly depending on the ILIM resistor and
any stray capacitance on the pin. To maximize this slew rate, minimize stray capacitance on this pin.
The duration of the synchronization pulse pulling ILIM/SYNC low shoud be between 50 ns and 100 ns. Longer
durations may limit the maximum obtainable duty cycle.
相關PDF資料
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