參數(shù)資料
型號(hào)： TPS3513DR
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 電源管理
英文描述： 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
封裝： GREEN, PLASTIC, MS-012AB, SOIC-14
文件頁(yè)數(shù)： 12/19頁(yè)
文件大?。?/td> 489K
代理商： TPS3513DR
SLVS313B – FEBRUARY 2001 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
UVLO thresholds are 4.45 V (on) and 3.65 V (off). Overcurrent protection (OCP) and overvoltage protection
(OVP) monitor 3.3 V, 5 V, and 12 V. When an OC or OV condition is detected, the power-good output (PGO) is
asserted low and the fault protection output (FPO) is latched high. PSON from low-to-high resets the latch. The
OCP function will be enabled 75 ms after PSON goes low, and a debounce of typically 38 ms. A built-in 2.3-ms
delay with 38-ms debounce from PSON to FPO output is enabled at turnoff.
An external resistor is connected between the RI pin and the GND pin. This will introduce an accurate I(ref) for
OCP function. The I(ref) range is from 12.5 A to 62.5 A. The formula for choosing RI resistor is V(RI)/I(ref). Three
OCP comparators and the I(ref) section are supplied by VS12. The current draw from the VS12 pin is less
than 1 mA.
The power good feature monitors PGI, 3.3 V and 5 V, and issues a power good signal when the output is ready.
The TPS3513 is characterized for operation from –40°C to 85°C.
Table 1. FUNCTION TABLE(1)
UV CONDITION
UV CONDITION 12 V
PGI
PSON
OV CONDITIONS
FPO
PGO
3.3 V / 5 V
OC Conditions
< 0.9 V
L
No
L
< 0.9 V
L
No
Yes
L
< 0.9 V
L
No
Yes
No
H
L
< 0.9 V
L
No
Yes
H
L
< 0.9 V
L
Yes
No
L
< 0.9 V
L
Yes
No
Yes
L
< 0.9 V
L
Yes
No
H
L
< 0.9 V
L
Yes
H
L
1.0 V < PGI < 1.1 V
L
No
L
1.0 V < PGI < 1.1 V
L
No
Yes
H
L
1.0 V < PGI < 1.1 V
L
No
Yes
No
H
L
1.0 V < PGI < 1.1 V
L
No
Yes
H
L
1.0 V < PGI < 1.1 V
L
Yes
No
L
1.0 V < PGI < 1.1 V
L
Yes
No
Yes
H
L
1.0 V < PGI < 1.1 V
L
Yes
No
H
L
1.0 V < PGI < 1.1 V
L
Yes
H
L
>1.2 V
L
No
L
H
>1.2 V
L
No
Yes
H
L
>1.2 V
L
No
Yes
No
H
L
>1.2 V
L
No
Yes
H
L
>1.2 V
L
Yes
No
L
>1.2 V
L
Yes
No
Yes
H
L
>1.2 V
L
Yes
No
H
L
>1.2 V
L
Yes
H
L
x
H
x
H
L
(1)
x = don't care, FPO = L means: fault is not latched, FPO = H means: fault is latched, PGO = L means: fault, PGO = H means: No fault
2
Copyright 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): TPS3513
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