參數(shù)資料
型號(hào): TPS3510P
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 3-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8
封裝: ROHS COMPLIANT, PLASTIC, DIP-8
文件頁數(shù): 15/18頁
文件大?。?/td> 528K
代理商: TPS3510P
TPS3510,TPS3511
PC POWER SUPPLY SUPERVISORS
SLVS312A – JULY 2000 – REVISED DECEMBER 2002
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
power supply remote on/off (PSON) and fault protect output (FPO)(continued)
When the FPO signal is held high due to an occurring fault condition, the fault status is latched and the outputs
of the main power rails should not deliver current but are held at 0 V. Toggling the power supply remote on/off
(PSON) from low to high resets the fault-protection latch. During this fault condition only the standby power is
not affected.
When PSON goes from high to low or low to high, the 38-ms debounce block is active to avoid a glitch on the
input that disables/enables the FPO output. During this period the under-voltage function is disabled for 75 ms
to prevent turnon failure. At turnoff, there is an additional delay of 2.3 ms from PSON to FPO.
Power should be delivered to the rails only if the PSON signal is held at ground potential, thus FPO is active-low.
The FPO pin can be connected to 5 V (or up to 15 V) through a pullup resistor.
undervoltage protection
The TPS3510/1 provides under-voltage protection (UVP) for the 3.3-V and 5-V rails. When an undervoltage
condition appears at either one of the 3.3-V (VS33) or 5-V (VS5) input pins for more than 146
s, the FPO output
goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high or VDD
is removed.
The need for undervoltage protection is often overlooked in off-line switching power supply system design. But
it is very important in battery-powered or hand-held equipment since the TTL or CMOS logic often results in
malfunction.
In flyback or forward-type off-line switching power supplies, usually designed for low power, the overload
protection design is very simple. Most of these types of power supplies are only sensing the input current for
an overload condition. The trigger point needs to be set much higher than the maximum load in order to prevent
false turnon.
However, this causes one critical problem. If the connected load is larger than the maximum allowable load but
smaller than the trigger point, the system always becomes overheated with failure and damage occurring.
overvoltage protection
The overvoltage protection (OVP) of TPS3510/1 monitors 3.3 V, 5 V, and 12 V (12 V is sensed via the VDD pin).
When an overvoltage condition appears at one of the 3.3-V, 5-V, or 12-V input pins for more than 73
s, the FPO
output goes high and PGO goes low. Also, this fault condition is latched until PSON is toggled from low to high
or VDD is removed. During fault conditions, most power supplies have the potential to deliver higher output
voltages than those normally specified or required. In unprotected equipment, it is possible for output voltages
to be high enough to cause internal or external damage of the system. To protect the system under these
abnormal conditions, it is common practice to provide overvoltage protection within the power supply.
Because TTL and CMOS circuits are very vulnerable to overvoltages, it is becoming industry standard to provide
overvoltage protection on all 3.3-V and 5-V outputs. However, not only the 3.3-V and 5-V rails for the logic circuits
on the motherboard need to be protected, but also the 12-V peripheral devices such as the hard disk, floppy
disk, and CD-ROM players etc., need to be protected.
short-circuit power supply turnon
During safety testing the power supply might have tied the output voltage direct to ground. If this happens during
the normal operating, this is called a short-circuit or over-current condition. When it happens before the power
supply turns on, this is called a short-circuit power supply turnon. It can happen during the design period, in the
production line, at quality control inspection or at the end user. The TPS3510/1 provides an undervoltage
protection function with a 75-ms delay after PSON is set low.
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