參數(shù)資料
型號: TPS2383BPMR
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64
封裝: GREEN, LQFP-64
文件頁數(shù): 5/27頁
文件大?。?/td> 415K
代理商: TPS2383BPMR
www.ti.com
I2C INTERFACE
START/STOP
TPS2383B
SLUS565G – JULY 2003 – REVISED AUGUST 2005
APPLICATION INFORMATION (continued)
The serial interface used in the TPS2383B is a standard two-wire I2C slave architecture core. The standard
bi-directional SDA lines of the I2C architecture are broken out into an independent input and output path. This
feature simplifies, earth grounded, controller applications that require opto-isolators to keep the 48-V return of the
ethernet power system floating. For applications where opto-isolation is not required, the bi-directional property of
the SDA line can be restored by connecting SDA_I to SDA_O. The SCL line is a unidirectional input only line as
the TPS2383B is always accesses as a slave device and it never controls the bus.
Data transfers that require a data-flow reversal on the SDA line are four-byte operations. This occurs during a
TPS2383B port read access cycle where a slave address byte is sent, followed by a port/register address byte
write. A second slave address byte is sent followed by the data byte read using the port/register setup from the
second byte in the sequence.
Data write transfers to the TPS2383B do not require a data-flow reversal and as such only a three-byte operation
is required. The sequence in this case is to send a slave address byte, followed by a write of the port/register
address followed by a write of the data byte for the addressed port.
The I2C access cycle consists of the following steps 1 through 7 and is also shown in Figure 4.
1. Start sequence (S)
2. Slave address field
3. Read/write
4. Acknowledge
5. Port/register address or data field
6. Acknowledge/not acknowledge
7. Stop sequence (P)
The I2C interface and the port read write registers are held in active reset until input voltage is within specification
and the internal POR timer has timed out.
The high-to-low transition of SDA while SCL is high defines the start condition. The low-to-high transition of SDA
while SCL is high defines the stop condition. The master device initiates all start and stop conditions.
A first serial packet enclosed within start and stop bits, consists of a seven-bit address field, read/write bit, and
the acknowledge bit. The acknowledge bit is always generated by the device receiving the address or data field.
Five of the seven address bits are used by the TPS2383B. The sixth and seventh bit is a placeholder for future
expansion. During a write operation to the TPS2383B from the master device, the data field is eight bits. During a
read operation where the TPS2383B is writing to the master device, the data field is also eight bits.
13
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