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參數(shù)資料
| 型號： | TPS2383BPM |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP64 |
| 封裝： | GREEN, LQFP-64 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大小： | 415K |
| 代理商： | TPS2383BPM |
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DATA READ CYCLE
TPS2383B
SLUS565G – JULY 2003 – REVISED AUGUST 2005
For a data read sequence, after the register acknowledge bit, the master device generates a Stop condition. This
is followed by a second Start condition, and retransmitting the device address as described in Chip Address
above. For this cycle, however, the R/W bit is set to a 1 to signal the read operation. The TPS2383B again
responds with an acknowledge pulse. The address acknowledge is then followed by sequentially presenting each
of the eight data bits on the SDA line (MSB first), to be read by the host device on the rising edges of SCL. After
eight bits are transmitted, the host acknowledges by pulling the SDA line high for one clock pulse. The completed
data transfer is terminated with the host generating a Stop condition.
Table 2. Register/Port Addressing
BIT
FUNCTION
STATE
D7
Future expansion
D6
Future expansion
000 = Control (common Write register)
D5
R2, register select MSB
001 = Port Status (per port Read register)
010 = Port Control (per port Write register)
D4
R1, register select
011 = A2D Register low byte (common read register)
100 = A2D Register high byte (common read register)
D3
R0, register select LSB
101 = Chip identification/revision (common read register)
000 = Port 1
D2
P2, port address MSB
001 = Port 2
010 = Port 3
011 = Port 4
D1
P1, port address
100 = Port 5
101= Port 6
110 = Port 7
D0
P0, port address LSB
111 = Port 8
Table 3. Common Control
Write Register, Register Address = 000 (Common Register)
BIT
FUNCTION
STATE
PRESET
STATE
D7
Jog-mode
0 = Normal mode
0
1 = Jog mode
D6
Jog
0 = Don’t jog
0
1 = Jog. This bit is self-clearing. It does not need to be reset to a 0
for each new jog.
D5
Bypass ramp
0 = Normal mode
0
1 = Bypass power–up ramp and powered mode for all ports
D4
Disconnect disable
0 = Normal mode
0
1 = Disable the effect of the logic signal from the Disconnect
detection circuits. This is an expansion function for future parts.
This bit should be set to a logic 1
D3
Bypass discovery
0 = Normal mode
0
1 = Bypass discovery mode.
D2
Bypass sample
0 = Normal mode
0
1 = Bypass current sample of all powered ports.
D1
Bypass classification
0 = Normal mode
0
1 = Bypass classification of all ports.
D0
Discovery fault disable
0 = Normal mode
0
1 = Disable the effect of the logic signal from the Discovery
circuits. This is an expansion function for future parts. This bit
should be set to a logic 1.
16
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