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參數(shù)資料
| 型號： | TPS2371D |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 14/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PWR INTRFCE SW FOR POE 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 應(yīng)用： | 用于以太網(wǎng)供電（PoE）設(shè)備的電源接口開關(guān) |
| 接口： | IEEE 802.3af |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 1013 (CN2011-ZH PDF) |
| 其它名稱： | 296-15960-5 |
TPS2371
SLUS566A JULY 2003 REVISED NOVEMBER 2003
4
www.ti.com
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
I/O
DESCRIPTION
CLASS
2
O
Sets classification level with a single resistor to VEE. A precision voltage of 10.0 V is applied to this pin during
classification. RCLASS values listed in Table 1.
DELAY(2)
7
I
UVLO turn-off delay programming. Connect a capacitor between VCC and this pin to program the UVLO
turn-off delay.
DET
3
O
Connect the 24.9k
detection resistor (RDET) between this pin and VDD.
EN_DC
6
O
Ties to dc-to-dc converter’s shutdown or soft-start pin. Sinks 80
A until the load capacitor is fully charged.
ILIM(1)
1
O
Sets startup current limit level with a resistor to VEE. If using CDC2DCIN > 180 F, IRUSH must be less than
400 mA. Extra capacitance on ILIM pin can cause oscillations in the current waveform.
RTN
5
O
Return pin. Connect this pin to input return side of the dc-to-dc converter.
VDD
8
I
Connection to PD input port positive voltage.
VEE
4
I
Input side power return for the controller.
NOTE 1:
I
INRUSH + 450 mA *
25 k
W
R
LIM
(1A)
NOTE 2:
T
DELAY +
100 ms
mF
C
DELAY
DETAILED PIN DESCRIPTIONS
ILIM (Pin 1)
Inrush current limiting pin. This pin is used to program the inrush current of the device. Due to the low UVLO
hysteresis of this device, a 1.0-
F capacitor from this pin to VEE is necessary to allow startup with 20 in series
with VDD as required by the IEEE standards. By placing a resistor to VEE from this pin, the inrush current into
the load will be limited via the following equation:
I
INRUSH + 450 mA *
25 k
W
R
LIM
(1A)
CLASS (Pin 2)
Classification pin. The PD can be optionally classified by adding a resistor from this pin to ground. The resistor
specific to each class is given in Table 1: PoE Classification Resistance Values.
DET (Pin3)
Detection pin. This pin is used to set up the detection resistance during PD detection. By tying a resistor, RDET,
from this pin to VDD, the user sets the detection resistance. It should be noted that the device itself looks like
approximately 1 M
of resistance in parallel with RDET.
VEE (Pin 4)
Negative supply to the device.
RET (Pin 5)
Negative supply to the load. This pin is the drain side of a FET between the RET pin and the VEE pin, providing
hot swap capabilities to the load. When the FET is switched on, there is approximately 300m
between this
pin and VEE.
(1)
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