參數(shù)資料
型號(hào)： TPS2346PWTR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 電源管理
英文描述： 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24
封裝： TSSOP-24
文件頁(yè)數(shù)： 17/30頁(yè)
文件大?。?/td> 490K
代理商： TPS2346PWTR
TPS2346
SLUS529 – MAY 2002
24
www.ti.com
APPLICATION INFORMATION
To complete the design of the power interface for the plug–in shown in the typical application diagram, assume
that a maximum slew rate of 1.5 A/ms is specified for each of the three positive-voltage loads. A value for
capacitor C2 must still be determined. Inspection of equation (4) indicates that, given the same di/dt requirement
on all supplies, the supply channel(s) with the lowest-value sense resistor dictates the minimum value for the
IRAMP capacitor. Therefore, the 5-V and 3.3-V supplies are suggested in this case for obtaining an initial
estimate for CIRAMP. Using the associated values, equation (4) produces the result shown in equation (5).
C
IRAMP2,3 +
68
67.5
(0.002
W)
1500 A s
^ 0.336 mF
A value of 0.33
F can be used, or the next available standard value of 0.39 F provides some margin for
capacitor and sense-resistor tolerances. In either case, equation (4) can be rewritten as equation (6), which is
used here to verify that the 5.15-V slew rate is still within specification.
di dt
x +
68
67.5
R
SNSx
C
IRAMPx
where:
RSNSx is in ohms,
CIRAMPx is the value suggested by equation (5) in microfarads, and
(di/dt)x is given in amps/second.
For a CIRAMP of 0.39 F, the maximum di/dt for the 5.15-V supply is approximately 860 mA/ms which is well
within the example requirement.
protection against faulted loads
The TPS2346 allows the time period of one IRAMP pulse for each back-end plane’s voltage to ramp-up to its
minimum level. After this delay period, the device latches off if an undervoltage fault is subsequently detected.
This nominal delay time, tTIMER, is set by the constant-current charging and subsequent discharging of CIRAMP,
and is therefore determined from equation (7).
t
TIMER + CIRAMP
1.4
1
58
) 1
1.8
where:
CIRAMP is in microfarads.
The resultant fault timer period should be sufficient for most applications; however, it is good design practice
to verify that the delay is long enough for each load.
(5)
(6)
(7)
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