
SETTING THE CURRENT-LIMIT CIRCUIT-BREAKER THRESHOLD
I
LMT +
R
ISET
50
10–6
R
ISENSE
(2)
SETTING THE POWER-GOOD THRESHOLD VOLTAGE
R
VSENSE_TOP +
V
O_min * 1.225
1.225
R
VSENSE_BOT
(3)
UNDERVOLTAGE LOCKOUT (UVLO)
POWER-UP CONTROL
SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006 ............................................................................................................................................... www.ti.com
pin. Once the gate has been pulled below approximately 1.5 V, this driver is disengaged and the UVLO driver
is enabled instead.
The current sensing resistor RISENSE and the current limit setting resistor RISET determine the current limit of the
channel, and can be calculated by the following equation:
Typically RISENSE is usually very small (0.001 to 0.1 ). If the trace and solder-junction resistances between the
junction of RISENSE and ISENSE and the junction of RISENSE and RISET are greater than 10% of the RISENSE value,
then these resistance values should be added to the RISENSE value used in the calculation above.
Table 3 shows some of the current-sense resistors available in the market.
Table 3. Some Current-Sense Resistors
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
0 to 1
WSL-1206, 0.05 1%
0.05
, 0.25 W, 1% resistor
1 to 2
WSL-1206, 0.025 1%
0.025
, 0.25 W, 1% resistor
2 to 4
WSL-1206, 0.015 1%
0.015
, 0.25 W, 1% resistor
Vishay Dale
4 to 6
WSL-2010, 0.010 1%
0.010
, 0.5 W, 1% resistor
6 to 8
WSL-2010, 0.007 1%
0.007
, 0.5 W, 1% resistor
8 to 10
WSR-2, 0.005 1%
0.005
, 0.5 W, 1% resistor
The two feedback resistors RVSENSE_TOP and RVSENSE_BOT connected between VO and ground form a resistor
divider, setting the voltage at the VSENSE pins. VSENSE voltage equals:
VI(SENSE) = VO
RVSENSE_BOT/(RVSENSE_TOP + RVSENSE_BOT)
This voltage is compared to an internal voltage reference (1.225 V ±2%) to determine whether the output voltage
level is within a specified tolerance. For example, given a nominal output voltage at VO, and defining VO_min as
the minimum required output voltage, then the feedback resistors are defined by:
Start the process by selecting a large standard resistor value for RVSENSE_BOT to reduce power loss. Then
RVSENSE_TOP can be calculated by inserting all of the known values into the equation above. When VO is lower
than VO_min, PWRGD is low as long as the controller is enabled.
The TPS2330/TPS2331 includes an undervoltage lockout (UVLO) feature that monitors the voltage present on
the VREG pin. This feature disables the external MOSFET if the voltage on VREG drops below 2.78 V (nominal)
and re-enables normal operation when it rises above 2.85 V (nominal). Because VREG is fed from IN through a
low-dropout voltage regulator, the voltage on VREG tracks the voltage on IN within 50 mV. While the
undervoltage lockout is engaged, GATE is held low by an internal PMOS pulldown transistor, ensuring that the
external MOSFET transistor remain off at the times, even if the power supply has fallen to 0 V.
The TPS2330/TPS2331 includes a 500-
s (nominal) start-up delay that ensures that internal circuitry has
sufficient time to start before the device begins turning on the external MOSFETs. This delay is triggered only
upon the rapid application of power to the circuit. If the power supply ramps up slowly, the undervoltage lockout
circuitry provides adequate protection against undervoltage operation.
14
Copyright 2000–2006, Texas Instruments Incorporated