參數(shù)資料
型號(hào): TPS2330IDRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
封裝: GREEN, PLASTIC, MS-012AB, SOIC-14
文件頁數(shù): 5/25頁
文件大小: 716K
代理商: TPS2330IDRG4
TIMER
OUTPUT-VOLTAGE SLEW-RATE CONTROL
dVs
dt
+
15 mA
C
gd
(1)
VREG CAPACITOR
GATE DRIVE CIRCUITRY
www.ti.com ............................................................................................................................................... SLVS277F – MARCH 2000 – REVISED NOVEMBER 2006
Table 2. Some Available N-Channel MOSFETs
CURRENT RANGE
PART NUMBER
DESCRIPTION
MANUFACTURER
(A)
IRF7601
N-channel, rDS(on) = 0.035 , 4.6 A, Micro-8
International Rectifier
MTSF3N03HDR2
N-channel, rDS(on) = 0.040 , 4.6 A, Micro-8
ON Semiconductor
0 to 2
IRF7101
Dual N-channel, rDS(on) = 0.1 , 2.3 A, SO-8
International Rectifier
MMSF5N02HDR2
Dual N-channel, rDS(on) = 0.04 , 5 A, SO-8
ON Semiconductor
IRF7401
N-channel, rDS(on) = 0.022 , 7 A, SO-8
International Rectifier
MMSF5N02HDR2
N-channel, rDS(on) = 0.025 , 5 A, SO-8
ON Semiconductor
2 to 5
IRF7313
Dual N-channel, rDS(on) = 0.029 , 5.2 A, SO-8
International Rectifier
SI4410
N-channel, rDS(on) = 0.020 , 8 A, SO-8
Vishay Dale
IRLR3103
N-channel, rDS(on) = 0.019 , 29 A, d-Pak
International Rectifier
5 to 10
IRLR2703
N-channel, rDS(on) = 0.045 , 14 A, d-Pak
International Rectifier
For most applications, a minimum capacitance of 50 pF is recommended to prevent false triggering. This
capacitor should be connected between TIMER and ground. The presence of an overcurrent condition on of the
TPS2330/31 causes a 50-
A current source to begin charging this capacitor. If the overcurrent condition persists
until the capacitor has been charged to approximately 0.5 V, the TPS2330/31 latches off the transistor and pulls
the FAULT pin low. The timer capacitor can be made as large as desired to provide additional time delay before
registering a fault condition. The time delay is approximately:
dt(sec) = C(TIMER)(F) × 10,000()
When enabled, the TPS2330/TPS2331 controllers supply the gate of an external MOSFET transistor with a
current of approximately 15
A. The slew rate of the MOSFET source voltage is thus limited by the gate-to-drain
capacitance Cgd of the external MOSFET capacitor to a value approximating:
If a slower slew rate is desired, an additional capacitance can be connected between the gate of the external
MOSFET and ground.
The internal voltage regulator connected to VREG requires an external capacitor to ensure stability. A 0.1-
F or
0.22-
F ceramic capacitor is recommended.
The TPS2330/TPS2331 includes four separate features associated with each gate-drive terminal:
A charging current of approximately 15 A is applied to enable the external MOSFET transistor. This current
is generated by an internal charge pump that can develop a gate-to-source potential (referenced to DISCH) of
9 V–12 V. DISCH must be connected to the external MOSFET source terminal to ensure proper operation of
this circuitry.
A discharge current of approximately 75 A is applied to disable the external MOSFET transistor. Once the
transistor gate voltage has dropped below approximately 1.5 V, this current is disabled and the UVLO
discharge driver is enabled instead. This feature allows the part to enter a low-current shutdown mode while
ensuring that the gate of the external MOSFET transistor remains at a low voltage.
During a UVLO condition, the gate of the MOSFET transistor is pulled down by an internal PMOS transistor.
This transistor continues to operate even if the voltage at IN is 0 V. This circuitry also helps hold the external
MOSFET transistor off when power is suddenly applied to the system.
During an overcurrent fault condition, the external MOSFET transistor that exhibited an overcurrent condition
is rapidly turned off by an internal pulldown circuit capable of pulling in excess of 400 mA (at 4 V) from the
Copyright 2000–2006, Texas Instruments Incorporated
13
Product Folder Link(s): TPS2330 TPS2331
相關(guān)PDF資料
PDF描述
TPS2331IPWG4 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO14
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