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參數(shù)資料
| 型號(hào)： | TPS2311IPWRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO20 |
| 封裝： | GREEN, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 644K |
| 代理商： | TPS2311IPWRG4 |
www.ti.com
ABSOLUTE MAXIMUM RATINGS
DISSIPATION RATING TABLE
RECOMMENDED OPERATING CONDITIONS
SLVS275G – FEBRUARY 2000 – REVISED NOVEMBER 2006
TIMER – A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning
off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which
charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker
latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to
restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly
recommended from TIMER to ground, to prevent any false triggering.
VREG – VREG is the output of an internal low-dropout voltage regulator, where IN1 is the input. The regulator is
used to generate a regulated voltage source, less than 5.5 V, for the device. A 0.1-
F ceramic capacitor should
be connected between VREG and ground to aid in noise rejection. In this configuration, upon disabling the
device, the internal low-dropout regulator will also be disabled, which removes power from the internal circuitry
and allows the device to be placed in low-quiescent-current mode. In applications where IN1 is less than 5.5 V,
VREG and IN1 may be connected together. However, under these conditions, disabling the device does not
place the device in low-quiescent-current mode, because the internal low-dropout voltage regulator is being
bypassed, thereby keeping internal circuitry operational. If VREG and IN1 are connected together, a 0.1-
F
ceramic capacitor between VREG and ground is not needed if IN1 already has a bypass capacitor of 1
F to
10
F.
VSENSE1, VSENSE2 – VSENSE1 and VSENSE2 can be used to detect undervoltage conditions on external
circuitry. If VSENSE1 senses a voltage below approximately 1.23 V, PWRGD1 is pulled low. Similarly, a voltage
less than 1.23 V on VSENSE2 causes PWRGD2 to be pulled low.
over operating free-air temperature range (unless otherwise noted) (1)(2)
VALUE
UNIT
VI(IN1), VI(ISENSE1), VI(VSENSE1), VI(VSENSE2), VI(ISET1), VI(ENABLE), VI(VREG)
–0.3 to 15
V
Input voltage range
VI(IN2), VI(ISENSE2), VI(ISET2)
–0.3 to 7
V
VO(GATE1)
–0.3 to 30
V
Output voltage range
VO(GATE2)
–0.3 to 22
V
VO(DISCH1), VO(PWRGD1), VO(PWRGD2), VO(FAULT), VO(DISCH2), VO(TIMER)
–0.3 to 15
V
I(GATE1), I(GATE2), I(DISCH1), I(DISCH2)
0 to 100
mA
Sink current range
I(PWRGD1), I(PWRGD2), I(TIMER), I(FAULT)
0 to 10
mA
Operating virtual junction temperature range, TJ
–40 to 100
°C
Storage temperature range, Tstg
–55 to 150
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltages are respect to DGND.
TA≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
PACKAGE
POWER RATING
ABOVE TA = 25°C
POWER RATING
PW-20
1015 mW
13.55 mW/
°C
406 mW
203 mW
MIN
NOM
MAX
UNIT
VI(IN1), VI(ISENSE1), VI(VSENSE1), VI(VSENSE2), VI(ISET1)
3
13
VI
Input voltage
V
VI(IN2), VI(ISENSE2), VI(ISET2), VI(VREG)
3
5.5
TJ
Operating virtual junction temperature
40
100
°C
4
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