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參數(shù)資料
| 型號： | TPS22949ADRGR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3 X 3 MM, GREEN, PLASTIC, SON-8 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 1001K |
| 代理商： | TPS22949ADRGR |
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SLVS908C – FEBRUARY 2009 – REVISED JANUARY 2010
www.ti.com
APPLICATION INFORMATION
Undervoltage Lockout (UVLO)
The undervoltage lockout turns off the switch if the input voltage drops below the undervoltage lockout threshold.
With the ON pin active, the input voltage rising above the undervoltage lockout threshold causes a controlled
turn-on of the switch, which limits current over-shoots. The TPS22949/TPS22949A also has a UVLO on the V+
bias voltage and keep the output of the LDO shut off until the internal circuitry is operating properly.
Fault Reporting
When an overcurrent, input undervoltage, or overtemperature condition is detected, OC is set active low to signal
the fault mode. OC is an open-drain MOSFET and requires a pullup resistor between VIN and OC. During
shutdown, the pulldown on OC is disabled, reducing current draw from the supply.
Current Limiting
When the switch current reaches the maximum limit, the TPS22949/TPS22949A operates in a constant-current
mode to prohibit excessive currents from causing damage. TPS22949/TPS22949A has a minimum current limit
of 100 mA.
Input Voltage
The input voltage (VIN) of the current limiter is set from 1.62 V to 4.5 V, however if both the current limiter and the
LDO are enabled, the user must be careful to keep the input voltage (VIN) greater than 1.8 V + (voltage drop
through the switch) + (voltage drop through the LDO); otherwise, the LDO does not have a high enough internal
input signal to operate properly.
A current limiter input voltage ramp time less than the blanking time (~10 ms typical) is recommended. If the
ramp time extends beyond the blanking period, then the current limiter goes into recycle, and the system may not
start or operate properly.
Input/Output Capacitors
Although an input capacitor is not required for stability of on the input pin (VIN), it is good analog design practice
to connect a 0.1-
μF to 1-μF low equivalent series resistance (ESR) capacitor across the IN pin input supply near
the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection,
and ripple rejection. A higher value capacitor may be necessary if large, fast rise time load transients are
anticipated, or if the device is located close to the power source. If source impedance is not sufficiently low, a
0.1-
μF input capacitor may be necessary to ensure stability. The V+ bias pin does not require an input capacitor
because it does not source high currents. However, if source impedance is not sufficiently low, a small 0.1-
μF
bypass capacitor is recommended.
A 0.1-
μF capacitor CCL, should be placed between VOUTCL and GND. This capacitor prevents parasitic board
inductances from forcing VOUTCL below GND when the switch turns off. For the TPS22949, the total output
capacitance must be kept below a maximum value, CCL(max), to prevent the part from registering an over-current
condition and turning off the switch. The maximum output capacitance can be determined from the following
formula:
CCL = ILIM(MAX) × tBLANK(MIN) ÷ VIN
Due to the integral body diode in the PMOS switch, a CIN greater than CCL is highly recommended. A CCL greater
than CIN can cause VOUTCL to exceed VIN when the system supply is removed. This could result in current flow
through the body diode from VOUTCL to VIN.
On TPS22949, a storage capacitor (CCL) at the output of the current limiter is recommended to provide enough
current to the LDO during the start-up sequence. The storage capacitor is needed to reduce the amount of inrush
current supplied through the current-limited load switch to the LDO during the power-up sequence (see
Figure 44). If the CCL capacitor is too small, the inrush current needed to start the LDO and charge CLDO could be
interpreted by the current limiter as an over-current and, therefore, trigger the current-limiting feature of the
switch. The switch would then try to limit the current to the 100-mA limit, and the user would see an undesired
drop on the supply line (see Figure 45).
18
Copyright 2009–2010, Texas Instruments Incorporated
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