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| 型號(hào)： | TPS2113ADRBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 3 X 3 MM, PLASTIC, SON-8 |
| 文件頁(yè)數(shù)： | 22/27頁(yè) |
| 文件大?。?/td> | 714K |
| 代理商： | TPS2113ADRBR |
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SBVS045B – MARCH 2004 – REVISED MARCH 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over recommended operating junction temperature, IO(OUT) = 0 A, and RILIM = 400 Ω, unless otherwise noted.
TPS2112A, TPS2113A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY AND LEAKAGE CURRENTS, Continued
EN = High (inactive), VI(IN1) = 5.5 V,
0.5
2
VI(IN2) = 3.3 V
Quiescent current from IN1 (standby)
mA
EN = High (inactive), VI(IN1) = 3.3 V,
1
VI(IN2) = 5.5 V
EN = High (inactive), VI(IN1) = 5.5 V,
1
VI(IN2) = 3.3 V
Quiescent current from IN2 (standby)
mA
EN = High (inactive), VI(IN1) = 3.3 V,
0.5
2
VI(IN2) = 5.5 V
Forward leakage current from IN1
EN = High (inactive), VI(IN1) = 5.5 V, IN2 open,
0.1
5
mA
(measured from OUT to GND)
VO(OUT) = 0 V (shorted), TJ = 25°C
Forward leakage current from IN2
EN = High (inactive), VI(IN2) = 5.5 V, IN1 open,
0.1
5
mA
(measured from OUT to GND)
VO(OUT) = 0 V (shorted), TJ = 25°C
Reverse leakage current to INx (measured
EN = High (inactive), VI(INx) = 0 V,
0.3
5
mA
from INx to GND)
VO(OUT) = 5.5 V, TJ = 25°C
STAT OUTPUT
Leakage current
VO(STAT) = 5.5 V
0.01
1
mA
Saturation voltage
II(STAT) = 2 mA, IN1 switch is on
0.13
0.4
V
Deglitch time (falling edge only)
150
ms
CURRENT LIMIT CIRCUIT
RILIM = 400 Ω
0.51
0.63
0.80
TPS2112A
A
RILIM = 700 Ω
0.30
0.36
0.50
Current limit accuracy
RILIM = 400 Ω
0.95
1.25
1.56
TPS2113A
A
RILIM = 700 Ω
0.47
0.71
0.99
Time for short-circuit output current to settle
Current limit settling time
td
1
ms
within 10% of its steady state value.
Input current at ILIM
VI(ILIM) = 0 V
–15
0
mA
VSNS COMPARATOR
VI(VSNS) ↑
0.78
0.80
0.82
VSNS threshold voltage
V
VI(VSNS) ↓
0.735
0.755
0.775
VSNS comparator hysteresis
30
60
mV
Deglitch of VSNS comparator (both
↑ ↓ )
90
150
220
ms
Input current
0 V
≤ VI(VSNS) ≤ 5.5 V
–1
1
mA
UVLO
Falling edge
1.15
1.25
IN1 and IN2 UVLO
V
Rising edge
1.30
1.35
IN1 and IN2 UVLO hysteresis
30
57
65
mV
Falling edge
2.4
2.53
Internal VDD UVLO (the higher of IN1 and
V
IN2)
Rising edge
2.58
2.8
Internal VDD UVLO hysteresis
30
50
75
mV
UVLO deglitch for IN1, IN2
Falling edge
110
ms
4
Copyright 2004–2010, Texas Instruments Incorporated
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