參數(shù)資料
型號(hào): TPS2071DAPG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 電源管理
英文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO32
封裝: GREEN, PLASTIC, HTSSOP-32
文件頁數(shù): 2/29頁
文件大?。?/td> 732K
代理商: TPS2071DAPG4
www.ti.com
ELECTRICAL CHARACTERISTICS
L(PG _ DLY )
ref
d
C
V
t
Ch arg e Current
=
ELECTRICAL CHARACTERISTICS
SLVS287B – SEPTEMBER 2000 – REVISED SEPTEMBER 2007
over recommended operating junction temperature range, 4.5 V
≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V,
ENx = 0 V, EN_REG = 0 V, BP_DIS = 0 V, CL(3.3V_OUT) = 10 μF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR
VO
Output voltage, dc
VI(BP) = 4.25 V to 5.5 V, IO = 5 mA to 100 mA
3.2
3.3
3.4
V
Dropout voltage
IO = 100 mA
0.6
V
Line regulation
VI(BP) = 4.25 V to 5.25 V, IO = 5 mA
0.1
%/V
Load regulation
VI(BP) = 4.25 V, IO = 5 mA to 100 mA
0.6%
IOS
Short-circuit current limit (1)
VI(BP) = 4.25 V, 3.3V_OUT connected to GND
0.12
0.2
0.3
A
VI(3.3V_OUT) = 3.3 V
10
Pulldown current through transistor at
mA
3.3V_OUTPUT (2)
VI(3.3V_OUT) = 1 V
5
f = 1 kHz, CL(3.3V_OUT) = 4.7 μF, ESR = 0.25 ,
PSRR
Power-supply ripple rejection(2)
40
dB
IO = 5 mA, VI(BP)PP = 100 mV
Low-level trip threshold voltage at PG
2.88
2.94
3
V
Vhys
Hysteresis voltage at PG(2)
50
100
mV
VOH
High-level output voltage at PG
4.25 V
≤ VI(BP) ≤ 5.25 V, IO = 2 mA
2.4
V
VOL
Low-level output voltage at PG
4.25 V
≤ VI(BP) ≤ 5.25 V, IO = 3.2 mA
0.4
V
Vref
Reference voltage at PG_DLY
1.22
V
Charge current at PG_DLY
3
μA
td
Delay time at PG (2) (3)
CL(PG_DLY) = 0.47 μF
190
ms
(1)
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
(2)
Specified by design, not tested in production.
(3)
The PG delay time (td) is calculated using the PG_DLY reference voltage and charge current:
over recommended operating junction temperature range, 4.5 V
≤ VI(BP) ≤ 5.5 V, 4.85 V ≤ VI(SP) ≤ 5.5 V, 6 V ≤ VI(VEXT) ≤ 9 V,
ENx = 0 V, EN_REG = 3.3 V, BP_DIS = 0 V, CL(SP) = 220 μF (unless otherwise noted))
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOLTAGE REGULATOR CONTROLLER
VI(VEXT) = 6 V, IO(VCP) = 5 mA,
VO(CP)
Output voltage, charge pump
10
V
C(CP_P) = 10 nF, C(VCP) = 100 nF
6 V
≤ VI(VEXT) ≤ 9 V, IO(VCP) = 5 mA,
fosc
Oscillator frequency(1)
850
kHz
VO(VCP) = 10 V
Sourcing
VI(VCP) = 9 V, VO(GATE) = 7.5 V, VI(SP) = 4.5 V
500
μA
Gate drive current
Sinking
VI(VCP) = 9 V, VO(GATE) = 5.5 V, VI(SP) = 5.5 V
1.5
mA
Open-loop gain (1)
VI(VEXT) = 6 V, 0.5 V ≤ VO(GATE) ≤ 9 V
80
dB
Reference voltage at VI(SP), using external
VI(VEXT) = 6 V to 9 V, IRLZ24N FET
4.9
5.1
5.25
V
regulator
Gate clamp voltage
Gate to SP
10
V
(1)
Specified by design, not tested in production.
10
Copyright 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): TPS2070 TPS2071
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